Abstract: An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or more specifiers. Each specifier relates to a different portion of the page, and maps from that portion of the page to a corresponding range of packet addresses. Accordingly, the unit allows for address translation to be performed with a sub-page granularity.

Abstract: A hardware trace unit is integrated into a computer system that has a main memory. The trace unit includes registers that contain information defining a location in main memory, and has an input connection. This is used to eavesdrop on communications in the computer system, thereby obtaining information about the state and/or operation of the system. A trigger mechanism then compares the information received against one or more trigger conditions, such as whether a particular event has occurred. Responsive to the trigger conditions being satisfied, the trace unit generates an output record containing diagnostic information. This is sent for storage in the main memory of the computer at the location defined in the registers.

Abstract: A memory access request handling unit is arranged between a source of memory access requests and a data storage element that is the target of the memory access requests. The memory access request handling unit comprises a queue made up of a number of queue elements, each being capable of temporarily storing one memory access request. Comparison logic is arranged to monitor a window of the queue and to select one or more of the queue elements, representing memory access requests not yet transmitted to the data storage element, for transmission to the data storage element. The selection is made on the basis of a comparison between the memory access requests held in the queue and one or both of a priority value set for each memory access request and a list of memory access requests that are currently pending at the data storage element, the list being maintained in a list store of the memory access request handling unit.

Abstract: A hardware trace unit is integrated into a computer system that has a main memory. The trace unit includes registers that contain information defining a location in main memory, and has an input connection. This is used to eavesdrop on communications in the computer system, thereby obtaining information about the state and/or operation of the system. A trigger mechanism then compares the information received against one or more trigger conditions, such as whether a particular event has occurred. Responsive to the trigger conditions being satisfied, the trace unit generates an output record containing diagnostic information. This is sent for storage in the main memory of the computer at the location defined in the registers.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: A multi-thread computer system comprising an array of thread units and associated sets of execution units. The thread units are designed to be interconnected in a one-dimensional array with other thread units of the array via respective multi-bit bi-directional communication paths for transferring threads and for relaying activity values between thread units. Each thread unit has a thread control unit. Each thread control unit has on its left side a first multi-bit input and a first multi-bit output, each connected to a first one of the bi-directional communication paths, and on its right side a second multi-bit input and a second multi-bit output, each connected to a second one of the bi-directional communication paths.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: An integrated solid state memory device includes addressable memory locations. In use, an address port receives an address identifying at least one memory location and associated verification information (e.g., parity or error correcting information) for verifying the address. Decoding logic is responsive to a received address to decode the address and verification logic is responsive to a received address and a received verification portion to verify the received address. By providing address verification within a solid state memory device, it is possible to ensure a higher security of operation of a computer system incorporating such a memory device, as errors which might develop, for example, between a memory controller and individual memory devices can be detected. As well as being useful for normal operation, such a memory device facilitates checking of the operating limits of a system as bus speeds and memory access speeds increase.

Abstract: In processor with multiple execution units and at least one instruction buffer the dispatch of instructions to available units is prioritised for multiple paths following a conditional branch. For example, instructions in the instruction buffer relating to a predicted path following a conditional branch can be dispatched to available execution units in preference to instructions relating to any other path, the instructions relating to any other paths being dispatched to any execution units remaining available. Compared to a processor with conventional predictive branch execution, prioritised dispatch of instructions in accordance with prediction priorities enables optimisation of the use of available execution units. There is a gain in efficiency where a non-predicted path proves to be the correct path without impacting efficiency where the predicted path proves to be the correct path. This net gain in efficiency can be achieved with a minimum of additional resources.

Abstract: A processing system includes a mechanical support structure and a number of processing modules. Each processing module includes a module connector for mounting the processing module with respect to the support structure and at least one optical transceiver for providing an optical data link between the processing module and a further processing module mounted with respect to the mechanical support structure.