Abstract: A magnetic angle measurement system having magnetic angle sensors, signal processing circuitry and a processor is disclosed. First signal processing circuitry receives a first subset of outputs of a first plurality of outputs from a first magnetic angle sensor and determines first magnetic angle data based on the received first subset of outputs. Second signal processing circuitry receives a second subset of the outputs from the first magnetic angle sensor and determines second magnetic angle data based on the received second subset of outputs. Third signal processing circuitry receives a second plurality of outputs from the second magnetic sensor and determines third magnetic angle data based on the received second plurality of outputs. The processor compares the magnetic angle data and determines a processing result based on the comparison, where fault tolerance resolution of the magnetic angle measurement system is based at least in part on the processing result.

Abstract: The present disclosure provides a method of providing quadrant information to a magnetic sensing device comprising a magnetic angle sensor, and in particular, a magnetic angle sensor configured to provide 180° absolute angle measurements, such as a 180° anisotropic magnetoresistive (AMR) angle sensor, such that the magnetic sensing device outputs an analog signal encoded with 360° information. In this respect, magnetic sensing device is provided with a magnetic angle sensor and a quadrant detector, which may be provided on the same substrate or two separate substrates, wherein the signal from the quadrant detector is encoded into the analog sine and cosine voltage outputs from the magnetic angle sensor such that the two analog outputs provide 360° angle information.

Abstract: A battery monitoring system and method are disclosed. A battery monitor compares data in parallel register files. If voltage deviation above a certain threshold is detected in one register file, the system generates an alert that a fault exists upstream in the system. In order to better detect errors, the system may intentionally alter the voltages on the batteries to be monitored.

Abstract: An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.

Abstract: A redundant analog-to-digital conversion system can include at least one input multiplexer, first and second redundant analog-to-digital converters, a comparison circuit and an output multiplexer. The at least one input multiplexer can receive a plurality of analog input signals and output at lest one multiplexed analog input signal. The first and second redundant analog-to-digital converters can convert the at least one multiplexed analog input signal to respectively generate first and second digital output signals, the first digital output having a greater digital resolution than the second digital output. The comparison circuit can produce a comparison output signal as a function of a comparison of a plurality of most significant corresponding bit pairs of the first and second digital output signals. The output multiplexer can produce a multiplexed output including information from the comparison output signal and one of the digital output signals.

Abstract: A battery monitoring system and method are disclosed. A battery monitor compares data in parallel register files. If voltage deviation above a certain threshold is detected in one register file, the system generates an alert that a fault exists upstream in the system. In order to better detect errors, the system may intentionally alter the voltages on the batteries to be monitored.

Abstract: A redundant analog-to-digital conversion system can include at least one input multiplexer, first and second redundant analog-to-digital converters, a comparison circuit and an output multiplexer. The at least one input multiplexer can receive a plurality of analog input signals and output at lest one multiplexed analog input signal. The first and second redundant analog-to-digital converters can convert the at least one multiplexed analog input signal to respectively generate first and second digital output signals, the first digital output having a greater digital resolution than the second digital output. The comparison circuit can produce a comparison output signal as a function of a comparison of a plurality of most significant corresponding bit pairs of the first and second digital output signals. The output multiplexer can produce a multiplexed output including information from the comparison output signal and one of the digital output signals.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

Abstract: An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.

Abstract: Embodiments may include a data receiver having input for a current signal. The data receiver may further include a current generator to generate a reference current for comparison against the input current signal. The data receiver may also include a data converter having an input coupled to an intermediate node of the data receiver, the data converter comprising a plurality of cascaded stages with intermediate nodes among the stages.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.