Abstract: An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.

Abstract: In embodiments, a wireless receiver employs a hardware-based Fast Fourier Transform (FFT) engine controlled by firmware. The FFT engine executes tasks stored in a task list. Each task is associated with a different portion of a signal, for example, one or more Orthogonal Frequency Division Modulated (OFDM) symbols. Each task may include configuration information for the FFT engine for configuring the engine to process the associated portion of the signal, a pointer to the portion to be processed, and another pointer to the memory for storing the output. The task list may be firmware controlled. Division of the FFT into a configurable hardware part driven by firmware to read and execute the tasks in the task list may speed up the FFT process and make it more flexible. A hardware beacon sorter may be coupled to the FFT engine to sort the sub-carriers according to their energies.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: A reference signal management (RSM) program executing on a mobile device detects multiple reference signals, allocates those reference signals into groups, and performs reference signal management functions using information conveyed in the reference signals. The RSM program detects both broadband and narrowband reference signals and maintains updated groups of reference signals that are transmitted from access points with independent configurations or different radio technologies. Battery power of the mobile device is efficiently used to manage reference signals in heterogeneous network environments by preventing unnecessary handoffs, overhead downloads, access probes and new registrations. Reference signals are managed from both synchronous and asynchronous sectors and in idle mode as well as in connected state mode.

Abstract: A method and apparatus are presented for compensating drifts in access terminals occurring during a sleep time. The method includes determining whether a sleep time exceeds a threshold, buffering time domain samples containing acquisition pilots and a paging channel, powering down RF circuitry in the access terminal after buffering samples, processing the samples to compensate for drift, and determining whether the access terminal was paged based upon the processed samples. The apparatus includes a digital front end, an FFT engine coupled to the digital front end, a symbol buffer coupled to the FFT engine, a processor coupled to the digital front end, FFT engine, and symbol buffer, and a memory coupled to the processor, the memory further comprising instructions for executing the method.

Abstract: A demodulation mask bitmap includes binary mask values. Each mask value corresponds to an input resource element to a demodulator. For each mask value of a first state, a demodulation engine of the demodulator is not clocked and the demodulator outputs a zero-valued resource element. For each mask value of a second state, the demodulation engine is clocked, the input resource element is demodulated, and the demodulator outputs a demodulated resource element. A demodulation mask bitmap is designed to mask pilot resource elements and corrupted resource elements. Power is conserved by not clocking the demodulation engine for corrupted and pilot resource elements. Subsequent LLR generation and decode operations are simplified. Decoder performance is improved because the decoder does not decode LLR values derived from corrupted resource elements and/or resource elements not relevant to the reconstruction of a communicated message.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

Abstract: A communications system and method for a wireless mobile device is provided. The method includes performing sleep mode operations in a device and performing wake-up operations with one or more base stations in view of the sleep mode operations in the device. The method also includes demodulating a communications channel for the device during sleep mode operations in the device and prior to synchronizing with the base stations.

Abstract: Techniques for transmitting data in a communication system are described. A packet may be partitioned into multiple subpackets, and each subpacket may be encoded separately. The subpackets may be mapped to resources assigned for transmission of the packet, with at least one subpacket being mapped to a subset of the assigned resources. The assigned resources may include multiple tiles, with each tile corresponding to a block of time frequency resources. The subpackets may be mapped to the tiles such that (i) the subpackets are mapped to equal number of tiles to achieve similar decoding performance, (ii) each subpacket is mapped to at least NMIN tiles, if available, to achieve a certain minimum diversity order for the subpacket, and/or (iii) each subpacket is mapped to a subset of the multiple tiles, if possible, so that the subpacket can be decoded without having to demodulate all of the tiles.

Abstract: Techniques for encoding and decoding data are described. In an aspect, multiple code rates for a forward error correction (FEC) code may be supported, and a suitable code rate may be selected based on packet size. A transmitter may obtain at least one threshold to use for code rate selection, determine a packet size to use for data transmission, and select a code rate from among the multiple code rates based on the packet size and the at least one threshold. In another aspect, multiple FEC codes of different types (e.g., Turbo, LDPC, and convolutional codes) may be supported, and a suitable FEC code may be selected based on packet size. The transmitter may obtain at least one threshold to use for FEC code selection and may select an FEC code from among the multiple FEC codes based on the packet size and the at least one threshold.

Abstract: Systems and techniques are disclosed relating to wireless communications. These systems and techniques involve wireless communications wherein a device may be configured to recover an information signal from a carrier using a reference signal, detect a frequency error in the information signal; and periodically tune the reference signal to reduce the frequency error.

Abstract: Techniques for segmented CDMA searching are disclosed. In one aspect, a searcher comprises a plurality of storage elements selectable for performing a plurality of segmentable search tasks, each storage element operable for storage of and access to state information for one of the plurality of search tasks. In another aspect, a first search task is interrupted in progress, the state information for the first task is stored, a second search task is performed, and the first search task is continued using the stored state information. In yet another aspect, a search task is segmented into smaller search segments, sized to fit within contiguous available time in the searcher. Various other aspects of the invention are also presented. These aspects have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.

Abstract: Techniques for increased finger demodulation capability in a hardware efficient manner are disclosed. In one aspect, I and Q samples are shifted into a parallel-accessible shift register. A plurality of chip samples are accessed from the shift register and operated on in parallel to produce a multi-chip result for a channel each cycle. These multi-chip results can be accumulated and output to a symbol-rate processor on symbol boundaries. The scheduling of shift register access, computation, and accumulation can be scheduled such that the hardware is time-shared to support a large number of channels. In another aspect, time-tracking of a large number of channels can be accommodated through channel-specific indexing of the contents of the shift register file. These aspects, along with various others also presented, provide for hardware efficient chip rate processing capability for a large number of channels, with a high degree of flexibility in deployment of those channels.

Abstract: Various techniques are disclosed for unambiguously determining and tracking frame offset in asynchronous wireless communication user equipment. The user equipment determines the unambiguous connection frame number of a downlink channel. The equipment then determines frame timing information for neighbor cells. The frame timing information for the primary common control physical channel and uplink dedicated physical channels is determined. The frame timing is determined as a coarse resolution frame offset in conjunction with a fine resolution chip offset. The frame numbering information for the uplink and downlink dedicated physical channels and the primary common control physical channel is also determined. Then the frame number and timing information is updated using a counter accurate to one chip resolution. The frame offset is updated if the number of chips underflows or overflows a predetermined window. Frame timing may be updated by updating only the fine chip offset or may be completely determined.

Abstract: Techniques for inner/outer loop tracking that is stable and provides desirable loop convergence characteristics are disclosed. In one aspect, the contribution from any one inner loop to the tracking function of the outer loop is limited, to prohibit any one received signal component from dominating the outer loop. In another aspect, the rate of outer loop tracking variation is controlled to provide inner and outer loop stability. Various other aspects are also presented. These aspects have the benefit of providing stable inner and outer loop control, as well as efficient convergence and tracking by the various loops, resulting in reduced frequency error and improved communication performance.

Abstract: Various techniques are disclosed for unambiguously determining and tracking frame offset in asynchronous wireless communication user equipment. The user equipment determines the unambiguous connection frame number of a downlink channel. The equipment then determines frame timing information for neighbor cells. The frame timing information for the primary common control physical channel and uplink dedicated physical channels is determined. The frame timing is determined as a coarse resolution frame offset in conjunction with a fine resolution chip offset. The frame numbering information for the uplink and downlink dedicated physical channels and the primary common control physical channel is also determined. Then the frame number and timing information is updated using a counter accurate to one chip resolution. The frame offset is updated if the number of chips underflows or overflows a predetermined window. Frame timing may be updated by updating only the fine chip offset or may be completely determined.

Abstract: Techniques for inner/outer loop tracking that is stable and provides desirable loop convergence characteristics are disclosed. In one aspect, the contribution from any one inner loop to the tracking function of the outer loop is limited, to prohibit any one received signal component from dominating the outer loop. In another aspect, the rate of outer loop tracking variation is controlled to provide inner and outer loop stability. Various other aspects are also presented. These aspects have the benefit of providing stable inner and outer loop control, as well as efficient convergence and tracking by the various loops, resulting in reduced frequency error and improved communication performance.

Abstract: Techniques for segmented CDMA searching are disclosed. In one aspect, a searcher comprises a plurality of storage elements selectable for performing a plurality of segmentable search tasks, each storage element operable for storage of and access to state information for one of the plurality of search tasks. In another aspect, a first search task is interrupted in progress, the state information for the first task is stored, a second search task is performed, and the first search task is continued using the stored state information. In yet another aspect, a search task is segmented into smaller search segments, sized to fit within contiguous available time in the searcher. Various other aspects of the invention are also presented. These aspects have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.