Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Abstract: The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 ? to about 800 ?. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Abstract: The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

Abstract: A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Abstract: A method is provided, the method comprising forming a first dielectric layer above a structure layer, the first dielectric layer having an upper portion. The method also comprises grading the upper portion of the first dielectric layer using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N2O) and molecular nitrogen (O2).

Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.

Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Abstract: A method is provided, the method including forming a first dielectric layer above a first structure layer, and forming a first opening in the first dielectric layer, the first opening having sidewalls. The method also includes forming a second dielectric layer on the sidewalls of the first opening.

Abstract: A method includes providing at least one wafer having a process layer formed thereon for polishing. The process layer is polished using a first polishing process that is associated with a slurry having a first abrasive particle size. The process layer is polished using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon for polishing. The polishing tool is adapted to polish the process layer using a first polishing process that is associated with a slurry having a first abrasive particle size. The polishing tool is adapted to polish the process layer using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size.