Abstract: A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.

Abstract: A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.

Abstract: A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.

Abstract: A mechanism for balancing message traffic in a multi-chassis fully interconnected computer system partitioned into multiple domains allows the system to identify I/O transactions, to route I/O transactions over inter-domain cables, and to route non-I/O transactions over intra-domain cables. This beneficially reduces message traffic congestion on intra-domain cables.

Abstract: In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i.e., it does not rely on immediately preceding write to determine where the data packet should be sent. Using “address aliasing”, CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.

Abstract: A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.

Abstract: A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.

Abstract: A mechanism for balancing message traffic in a multi-chassis fully interconnected computer system partitioned into multiple domains allows the system to identify I/O transactions, to route I/O transactions over inter-domain cables, and to route non-I/O transactions over intra-domain cables. This beneficially reduces message traffic congestion on intra-domain cables.

Abstract: In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i.e., it does not rely on immediately preceding write to determine where the data packet should be sent. Using “address aliasing”, CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.

Abstract: A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.

Abstract: A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.