Abstract: Gate and fin trim isolation for advanced integrated circuit structure fabrication is described. For example, a method of fabricating an integrated circuit structure includes forming a plurality of fins along a first direction, removing a portion of one of the plurality of fins to form a trench, forming an isolation structure in the trench, the isolation structure extending above the one of the plurality of fins, forming a gate structure over the plurality of fins, the gate structure along a second direction orthogonal to the first direction, forming a dielectric spacer along sidewalls of the gate structure and the isolation structure, and, subsequent to forming the dielectric spacer, forming epitaxial source or drain structures in or on the plurality of fins.

Abstract: Disclosed herein are line patterning techniques for integrated circuit (IC) devices, as well as related devices and assemblies In some embodiments, a patterned line region of an IC device may include: a first conductive line; a second conductive line parallel to the first conductive line; a conductive bridge between the first conductive line and the second conductive line, wherein the conductive bridge is coplanar with the first conductive line and the second conductive line; and pitch-division artifacts.