Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

Abstract: In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed.

Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.

Abstract: In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.

Abstract: An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a processing device. Available options for a processor are determined by initialization code. And based on platform electrical capabilities, an optimal one of the multiple current configuration options is selected. Moreover, during runtime another current configuration is dynamically selected based on current configuration considerations to provide high flexibility and best possible performance per part and computing platform.