Abstract: A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.

Abstract: A chemical-mechanical planarization (CMP) process is provided whereby cyclical pressure means varies the force against the wafer and polishing pad during the planarizing operation with the planarizing pad specially defined to have a relaxation time which is correlated with the force cycle so that the planarizing is enhanced. The relaxation time of the pad is greater than the downward an/or upward force cycle time on the wafer or pad and provides a planarizing process wherein the height of the pad during planarization is intermediate between a decompressed pad position and a compressed pad position typically encountered in a conventional CMP process.

Abstract: A system for polishing a surface. The surface is positioned in contact with a rotating table having a polishing slurry or compound applied to a table surface. The pattern formed in the polishing compound as the table is rotated is monitored, and when the pattern dimensions reach a predetermined size, indicating a polished end point, the polisher ends polishing.

Abstract: The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production.

Abstract: A process for forming raised source/drain junctions using CMP (Chemical Mechanical Polishing) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by gate conductors and by raised STI (Shallow Trench Isolation) which also reduces leakage current through the devices and improves the threshold voltage control. The process uses a salicide gate conductor, and uses conventional polysilicon deposition, CMP, and recess steps to form the raised source/drain junctions, such that it is readily implemented in commercially feasible manufacturing processes.