Abstract: A method for controlling an etch process comprises providing a wafer having at least a first layer and a second layer formed over the first layer. The thickness of the second layer is measured. An etch selectivity parameter is determined based on the measured thickness of the second layer. An operating recipe of an etch tool is modified based on the etch selectivity parameter. A processing line includes an etch tool, a first metrology tool, and a process controller. The etch tool is adapted to etch a plurality of wafers based on an operating recipe, each wafer having at least a first layer and a second layer formed over the first layer. The first metrology tool is adapted to measure a pre-etch thickness of the second layer. The process controller is adapted to determine an etch selectivity parameter based on the measured pre-etch thickness of the second layer and modify the operating recipe of the etch tool based on the etch selectivity parameter.

Abstract: In one illustrative embodiment, a system is comprised of a semiconductor processing tool, an etcher, a metrology tool, and a controller. The semiconductor processing tool is capable of forming a process layer above a semiconducting substrate. The etcher is capable of removing at least a portion of the process layer. The metrology tool is capable of measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. The controller is capable of comparing the first depth to a desired depth, and varying the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region in response to the first depth being different from the desired depth.

Abstract: A method for monitoring consumable performance in a processing tool comprises storing a performance model of the processing tool; receiving a consumable item characteristic of a consumable item in the processing tool; determining a predicted processing rate for the processing tool based on the consumable item characteristic and the performance model; determining an actual processing rate of the processing tool; and determining a replacement interval for the consumable item based on at least the actual processing rate. A processing system includes a processing tool and an automatic process controller. The processing tool is adapted to process wafers and includes a consumable item.

Abstract: A processing line includes a deposition tool, a metrology tool and a controller. The deposition tool is adapted to form a polysilicon layer on a wafer in accordance with a recipe. The metrology tool is adapted to measure a grain size of the polysilicon layer. The controller is adapted to modify the recipe for subsequently formed polysilicon layers based on the measured grain size. A method for controlling a deposition process includes forming a polysilicon layer on a wafer in accordance with a recipe; measuring a grain size of the polysilicon layer; and changing the recipe for subsequently formed polysilicon layers based on the measured grain size.

Abstract: A method includes measuring a surface non-uniformity of a wafer. A current state of an etch processing tool is determined. The surface non-uniformity of the wafer is compared with the current state of the processing tool. An operating parameter of the processing tool is adjusted based on the comparison of the surface non-uniformity of the wafer with the current state of the processing tool. A system includes a processing tool, a plurality of measuring devices, and a process controller. The processing tool is adapted for etch processing of a wafer. The plurality of measuring devices measure a surface non-uniformity of the wafer and determine a current state of the processing tool. The process controller compares the surface non-uniformity of the wafer with the current state of the processing tool and adjusts an operating parameter of the processing tool based on the comparison.

Abstract: A method and apparatus for controlling photoresist baking processes. A wafer is provided with the wafer having a layer of photoresist thereon. A first thickness of the photoresist layer is measured, and a first fourier transform infrared (FTIR) spectra of the photoresist layer is generated. Based on the first thickness and first FTIR spectra, a bake time and bake temperature is determined. The wafer is then baked at the bake temperature for the bake time.

Abstract: In one illustrative embodiment, the method disclosed herein comprises forming a process layer above a semiconducting substrate, forming a layer of photoresist above the process layer, removing the layer of photoresist by performing an etching process, and determining an endpoint of the etching process based upon a temperature of the substrate.

Abstract: The present invention is directed to the field of semiconductor processing and, more particularly, to a method of planarizing or polishing process layers formed above a surface of a semiconducting substrate. In one illustrative embodiment, the method comprises determining the thickness of a process layer formed above a semiconducting substrate and determining a polishing recipe for said process layer based upon the measured thickness of said process layer.

Abstract: A method includes providing a first wafer having at least one process layer formed thereon. A portion of a first process layer is removed using a polishing process. A portion of at least one of the first process layer and a second process layer is removed using a buffing process for a pre-selected duration of time. A buffed surface of at least one of the first process layer and the second process layer is inspected to determine a post-buff defect density for the inspected process layer. The duration of the buffing process is adjusted for a second wafer based on the determined post-buff defect density of the inspected process layer. A system includes a processing tool, at least one metrology tool, and a process controller. The processing tool is adapted to remove at least a portion of a first process layer of a first wafer using a buffing process for a pre-selected duration of time.

Abstract: The present invention is directed to semiconductor processing operations, and, more particularly, to a method and system for adjusting the thickness of process layers based upon the planarization efficiency of polishing operations. In one embodiment, the invention comprises determining the planarization efficiency of polishing operations, and adjusting the manufactured thickness of a process layer based upon the determined planarization efficiency.

Abstract: A method of controlling surface non-uniformity of a process layer includes receiving a first lot of wafers, and polishing a process layer of the first lot of wafers. A control variable of the polishing operations is measured after the polishing is performed on the process layer. A first adjustment input for an arm oscillation length of a polishing tool is determined based on the measurement of the control variable. A process layer of a second lot of wafers is polished using the adjustment input for the arm oscillation length. A controller for controlling surface non-uniformity of a process layer includes an optimizer and an interface. The optimizer is adapted to determine a first adjustment input for arm oscillation length of a polishing tool based on a measurement of a control variable from a first lot of wafers. The interface is adapted to provide the first adjustment input to the polishing tool for polishing a second lot of wafers.

Abstract: The present invention is directed to the field of semiconductor processing and, more particularly, to a method of planarizing or polishing process layers formed above a surface of a semiconducting substrate. In one illustrative embodiment, the method comprises determining the thickness of a process layer formed above a semiconducting substrate and determining a polishing recipe for said process layer based upon the measured thickness of said process layer.

Abstract: The present invention is directed to semiconductor processing operations, and, more particularly, chemical mechanical polishing operations. The present invention is comprised of a method for qualifying new polishing pads used in a polishing tool without the necessity of polishing test wafers.

Abstract: The present invention is directed to the field of semiconductor processing and, more particularly, to a method of planarizing or polishing process layers formed above a surface of a semiconducting substrate. In one illustrative embodiment, the method comprises determining the thickness of a process layer formed above a semiconducting substrate and determining a polishing recipe for said process layer based upon the measured thickness of said process layer.

Abstract: A method, system, and memory storage medium for reducing variation of interconnect resistance of integrated circuits are provided. Interconnects are formed by a damascene process in which trenches are formed in an interlevel dielectric. The dimensions of the trenches are then measured. The dimension measurement results and the resistivity of the interconnect material are used to calculate a target thickness of interconnect material within the trench that gives a predetermined interconnect resistance. Interconnect material is then deposited within the trenches and upon the interlevel dielectric. A chemical-mechanical polishing process, which is used to remove interconnect material external to the trench, is then adjusted to leave the target thickness of interconnect material such that the completed interconnects have the predetermined resistance. Optionally, the resistance of the interconnects on the completed integrated circuits may be measured and compared to the predetermined interconnect resistance.