Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

Abstract: A digital-to-analogue conversion arrangement is disclosed which includes first and second groups of the same number of bi-directional bufferless digital-to-analogue converters. The output of at least one converter in each group is connected to a respective capacitive load (CLOAD, CLOAD?). During a calibration phase of operation the converter inputs receive first and second different codes representing the same output level. The arrangement also includes a respective switched capacitor network connected to each converter output, a comparator for comparing the output voltages of the first and second groups, and a control circuit. The control circuit controls the capacitor networks in response to the comparator so as to make the output voltages of the first and second groups substantially equal.

Abstract: A digital-to-analogue conversion arrangement is disclosed which includes first and second groups of the same number of bi-directional bufferless digital-to-analogue converters. The output of at least one converter in each group is connected to a respective capacitive load (CLOAD, CLOAD?). During a calibration phase of operation the converter inputs receive first and second different codes representing the same output level. The arrangement also includes a respective switched capacitor network connected to each converter output, a comparator for comparing the output voltages of the first and second groups, and a control circuit. The control circuit controls the capacitor networks in response to the comparator so as to make the output voltages of the first and second groups substantially equal.

Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.