Abstract: An asynchronous circuit which includes a first circuit suitable for receiving, from a first other circuit, a first data input signal, and for generating a first acknowledgement of receipt signal and a first data output signal; a second circuit suitable for receiving, from a second other circuit, a second data input signal, and for generating a second acknowledgement of receipt signal and a second data output signal, the second circuit being functionally equivalent to the first circuit; a comparator suitable for detecting an inconsistency between the first and second data input or output signals; and at least one circuit for pausing an acknowledgement of receipt suitable for preventing the propagation of the first and second acknowledgement of receipt signals towards the first and second other circuits if an inconsistency is detected by the comparator.

Abstract: An asynchronous circuit which includes a first circuit suitable for receiving, from a first other circuit, a first data input signal, and for generating a first acknowledgement of receipt signal and a first data output signal; a second circuit suitable for receiving, from a second other circuit, a second data input signal, and for generating a second acknowledgement of receipt signal and a second data output signal, the second circuit being functionally equivalent to the first circuit; a comparator suitable for detecting an inconsistency between the first and second data input or output signals; and at least one circuit for pausing an acknowledgement of receipt suitable for preventing the propagation of the first and second acknowledgement of receipt signals towards the first and second other circuits if an inconsistency is detected by the comparator.