Patents by Inventor Jeremy Mah
Jeremy Mah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9930222Abstract: A method includes determining whether to switch from a first input video signal to a second input video signal. Upon switching from a first input video signal to a second input video signal, determining whether the current displayed frame has terminated. If the current displayed frame has terminated, process the second video input signal and load data corresponding to the second video input signal from the timing generator, scale and pixel clock registers correspondingly into the timing generator, scaler and pixel clock. Generate a clock signal for the second input video signal. Calculate generator parameter(s) corresponding to the second input video signal. Generate timing control signals for the second input video signal. Determine if a new frame of the second input video signal has occurred. Provide timing control signals and pixel data for the video to be displayed and corresponding the second input video signal.Type: GrantFiled: February 9, 2017Date of Patent: March 27, 2018Assignee: INTERSIL AMERICAS LLCInventors: Jeremy Mah, Morgan Tang, Hyoungyon Han
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Publication number: 20170264793Abstract: A method includes determining whether to switch from a first input video signal to a second input video signal. Upon switching from a first input video signal to a second input video signal, determining whether the current displayed frame has terminated. If the current displayed frame has terminated, process the second video input signal and load data corresponding to the second video input signal from the timing generator, scale and pixel clock registers correspondingly into the timing generator, scaler and pixel clock. Generate a clock signal for the second input video signal. Calculate generator parameter(s) corresponding to the second input video signal. Generate timing control signals for the second input video signal. Determine if a new frame of the second input video signal has occurred. Provide timing control signals and pixel data for the video to be displayed and corresponding the second input video signal.Type: ApplicationFiled: February 9, 2017Publication date: September 14, 2017Applicant: Intersil Americas LLCInventors: Jeremy MAH, Morgan TANG, Hyoungyon HAN
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Patent number: 9710191Abstract: Data associated with a logical block address (LBA) may be received from a host system to be stored in the memory array. The LBA may be translated to a physical block address (PBA) by determining a first portion of the PBA and a second portion of the PBA. The data from the host system may be stored in the buffer space after determining the first portion of the PBA and before determining the second portion of the PBA. The data from the buffer space may be flushed to the memory array after determining the second portion of the PBA.Type: GrantFiled: April 13, 2016Date of Patent: July 18, 2017Assignee: MONTEREY RESEARCH, LLCInventors: Frank Edelhaeuser, Clifford A. Zitlaw, Jeremy Mah
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Patent number: 9317445Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.Type: GrantFiled: February 11, 2013Date of Patent: April 19, 2016Assignee: Cypress Semiconductor CorporationInventors: Frank Edelhaeuser, Clifford A Zitlaw, Jeremy Mah
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Publication number: 20140351466Abstract: According to one exemplary embodiment, a system is provided. The system includes a system bridge, a host module including a central processing unit (CPU) coupled to the system bridge, a scalable serial bus coupled to the system bridge, a client controller coupled to the system bridge via the scalable serial bus, and first and second clients coupled to the client controller. The client controller is configured to interpret a communication received from the CPU and to provide the communication to the first client or to the second client based on a content of the communication. The scalable serial bus is configured such that each of the first and second clients have access to the scalable serial bus during respective time slots. The scalable serial bus is configured to scale at least one of a data transfer rate of the scalable serial bus, a number of channels on the scalable serial bus, or a bus width of the scalable serial bus.Type: ApplicationFiled: August 6, 2014Publication date: November 27, 2014Inventors: Stephan Rosner, Qamrul Hasan, Jeremy Mah
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Patent number: 8819326Abstract: According to one exemplary embodiment, a host/client system includes a host module, which includes a CPU coupled to a system bridge. The host/client system further includes at least one client having an integrated interface, where the integrated interface is coupled to the system bridge through a scalable serial bus. The system bridge and the integrated interface enable high bandwidth communication between the CPU and the at least one client through the scalable serial bus, thereby allowing control of bus width between the host module and the client.Type: GrantFiled: December 12, 2006Date of Patent: August 26, 2014Assignee: Spansion LLCInventors: Stephan Rosner, Qamrul Hasan, Jeremy Mah
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Patent number: 8386736Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.Type: GrantFiled: December 18, 2008Date of Patent: February 26, 2013Assignee: Spansion LLCInventors: Frank Edelhaeuser, Clifford A Zitlaw, Jeremy Mah
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Patent number: 8239637Abstract: A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.Type: GrantFiled: January 19, 2007Date of Patent: August 7, 2012Assignee: Spansion LLCInventors: Roger Isaac, Stephan Rosner, Qamrul Hasan, Jeremy Mah
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Patent number: 8230154Abstract: A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.Type: GrantFiled: January 19, 2007Date of Patent: July 24, 2012Assignee: Spansion LLCInventors: Roger Isaac, Stephan Rosner, Qamrul Hasan, Jeremy Mah
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Patent number: 7813459Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.Type: GrantFiled: October 3, 2005Date of Patent: October 12, 2010Assignee: Spansion LLCInventors: Qamrul Hasan, Stephan Rosner, Jeremy Mah
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Publication number: 20100161935Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Inventors: Frank EDELHAEUSER, Clifford A. ZITLAW, Jeremy MAH
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Patent number: 7639768Abstract: In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.Type: GrantFiled: May 1, 2006Date of Patent: December 29, 2009Assignee: Spansion LLCInventors: Qamrul Hasan, Jeremy Mah, Stephan Rosner
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Publication number: 20080177931Abstract: A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.Type: ApplicationFiled: January 19, 2007Publication date: July 24, 2008Applicant: SPANSION LLCInventors: Roger Isaac, Stephan Rosner, Qamrul Hasan, Jeremy Mah
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Publication number: 20080177930Abstract: A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.Type: ApplicationFiled: January 19, 2007Publication date: July 24, 2008Applicant: SPANSION LLCInventors: Roger Isaac, Stephan Rosner, Qamrul Hasan, Jeremy Mah
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Patent number: 7404026Abstract: A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.Type: GrantFiled: April 10, 2006Date of Patent: July 22, 2008Assignee: Spansion LLCInventors: Qamrul Hasan, Jeremy Mah, Stephan Rosner, Roger Dwain Isaac
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Publication number: 20070239918Abstract: A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.Type: ApplicationFiled: April 10, 2006Publication date: October 11, 2007Inventors: Qamrul Hasan, Jeremy Mah, Stephan Rosner, Roger Isaac
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Publication number: 20070076830Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.Type: ApplicationFiled: October 3, 2005Publication date: April 5, 2007Inventors: Qamrul Hasan, Stephan Rosner, Jeremy Mah
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Publication number: 20050163401Abstract: A display image enhancement apparatus and method are disclosed for use in generating additional pixel data from input image data, where a window of input pixel data is used to generate data for an additional pixel to be placed substantially in the center of the window. The display image enhancement apparatus includes memory elements that is capable of receiving a chain of input pixel data and storing at least the window of input pixel data, where the window of input pixels includes a plurality of pixel pairs each of which respectively represents an angle of correlation. The display image enhancement apparatus also includes instant angle detection circuitry capable of receiving the input pixel data stored in the memory elements and determining an instant angle having the highest correlation based on differential values of at least some of the pixel pairs, where a differential value is the difference between the values of pixels in a pixel pair.Type: ApplicationFiled: January 28, 2004Publication date: July 28, 2005Inventors: Seong Park, Jeremy Mah, Hiroshi Kanekura