Patents by Inventor Jeremy Mark Goldblatt
Jeremy Mark Goldblatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9762274Abstract: An apparatus includes an elliptical inductance-capacitance (LC) filter and a resistive-capacitive (RC) notch filter serially coupled to the elliptical LC filter. The elliptical LC filter and the RC notch filter are configured to filter a radio-frequency (RF) signal received by a feedback receive path.Type: GrantFiled: March 20, 2015Date of Patent: September 12, 2017Assignee: QUALCOMM IncorporatedInventors: Shailesh Shekhar Rai, Mahim Ranjan, Jeremy Mark Goldblatt, Frederic Bossu, Vijay Chellappa
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Patent number: 9531337Abstract: Removing common-mode current from a pair of complementary current signals, including: generating a common-mode voltage of the pair of complementary current signals including at least a first current signal and a second current signal; measuring and outputting a difference voltage between the generated common-mode voltage and a common-mode reference voltage; and removing at least a portion of the common-mode current from the first current signal and the second current signal based on the difference voltage.Type: GrantFiled: January 22, 2015Date of Patent: December 27, 2016Assignee: QUALCOMM IncorporatedInventors: Minghui Chen, Mahim Ranjan, Jeremy Mark Goldblatt, Frederic Bossu
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Patent number: 9356586Abstract: A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.Type: GrantFiled: March 12, 2013Date of Patent: May 31, 2016Assignee: QUALCOMM IncorporatedInventor: Jeremy Mark Goldblatt
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Patent number: 9263990Abstract: An impedance transformer for use with a quadrature passive mixer is disclosed. In an exemplary embodiment, an apparatus includes a mixer configured to generate an up-converted signal at a mixer output port in response to local oscillator (LO) signals, and an impedance transformer configured to provide a complex impedance at the mixer output port. The complex impedance configured to generate a selected level of the reverse isolation for the mixer thereby generating a selected amplitude flatness symmetry characteristic for the up-converted signal.Type: GrantFiled: May 21, 2013Date of Patent: February 16, 2016Assignee: Qualcomm IncorporatedInventor: Jeremy Mark Goldblatt
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Publication number: 20150349821Abstract: An apparatus includes an elliptical inductance-capacitance (LC) filter and a resistive-capacitive (RC) notch filter serially coupled to the elliptical LC filter. The elliptical LC filter and the RC notch filter are configured to filter a radio-frequency (RF) signal received by a feedback receive path.Type: ApplicationFiled: March 20, 2015Publication date: December 3, 2015Inventors: Shailesh Shekhar Rai, Mahim Ranjan, Jeremy Mark Goldblatt, Frederic Bossu, Vijay Chellappa
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Publication number: 20150349733Abstract: Removing common-mode current from a pair of complementary current signals, including: generating a common-mode voltage of the pair of complementary current signals including at least a first current signal and a second current signal; measuring and outputting a difference voltage between the generated common-mode voltage and a common-mode reference voltage; and removing at least a portion of the common-mode current from the first current signal and the second current signal based on the difference voltage.Type: ApplicationFiled: January 22, 2015Publication date: December 3, 2015Inventors: Minghui Chen, Mahim Ranjan, Jeremy Mark Goldblatt, Frederic Bossu
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Patent number: 9088285Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.Type: GrantFiled: June 25, 2013Date of Patent: July 21, 2015Assignee: QUALCOMM IncorporatedInventors: Jeremy Mark Goldblatt, Devavrata Vasant Godbole, Hsuanyu Pan
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Patent number: 9020458Abstract: A passive mixer with channel impedance equalization is disclosed. In an exemplary embodiment, an apparatus includes replica devices configured to generate replica output signals and an error amplifier configured to generate bias signals based on the replica output signals. The bias signals are configured to equalize on-state channel impedances associated with a mixer.Type: GrantFiled: May 23, 2013Date of Patent: April 28, 2015Assignee: QUALCOMM IncorporatedInventor: Jeremy Mark Goldblatt
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Publication number: 20140376683Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Jeremy Mark Goldblatt, Devavrata Vasant Godbole, Hsuanyu Pan
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Publication number: 20140361847Abstract: A low loss multiple output switch with integrated distributed attenuation is disclosed. In an exemplary embodiment, an apparatus includes a switchable shunt network having an input terminal and a plurality of network output terminals, the switchable shunt network comprising selectable signal paths that connect the input terminal to the network output terminals. The apparatus also includes selectable shunt impedances connected to the selectable signal paths to adjust parasitic loading on the selectable signal paths.Type: ApplicationFiled: June 5, 2013Publication date: December 11, 2014Applicant: QUALCOMM IncorporatedInventors: Jeremy Mark GOLDBLATT, Haigang FENG
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Publication number: 20140348218Abstract: A passive mixer with channel impedance equalization is disclosed. In an exemplary embodiment, an apparatus includes replica devices configured to generate replica output signals and an error amplifier configured to generate bias signals based on the replica output signals. The bias signals are configured to equalize on-state channel impedances associated with a mixer.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Applicant: QUALCOMM IncorporatedInventor: Jeremy Mark Goldblatt
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Publication number: 20140347117Abstract: An impedance transformer for use with a quadrature passive mixer is disclosed. In an exemplary embodiment, an apparatus includes a mixer configured to generate an up-converted signal at a mixer output port in response to local oscillator (LO) signals, and an impedance transformer configured to provide a complex impedance at the mixer output port. The complex impedance configured to generate a selected level of the reverse isolation for the mixer thereby generating a selected amplitude flatness symmetry characteristic for the up-converted signal.Type: ApplicationFiled: May 21, 2013Publication date: November 27, 2014Applicant: QUALCOMM IncorporatedInventor: Jeremy Mark Goldblatt
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Publication number: 20140266307Abstract: A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventor: Jeremy Mark Goldblatt
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Publication number: 20140103984Abstract: Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverters may be coupled to at least two dynamic logic cells of the plurality of dynamic logic cells. Each inverter may be configured to output a twenty-five percent duty cycle clock signal.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jeremy Mark Goldblatt, Sameer V. Vora
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Patent number: 6323725Abstract: A bias cell for use in biasing all NMOS differential pair is configured to substantially eliminate variations in transconductance caused by body effects. In one example, a voltage threshold mismatch between NMOS devices of the bias cell is substantially eliminated to thereby reduce variations in transconductance caused by body effects. To reduce the voltage threshold mismatch, the bias cell includes a transconductance-setting resistor connected between gates of a pair of current source devices. Circuitry is connected to the resistor for applying a voltage across the resistor. A bias line connects a signal output from the bias circuit to the differential pair.Type: GrantFiled: March 31, 1999Date of Patent: November 27, 2001Assignee: Qualcomm IncorporatedInventors: Jeremy Mark Goldblatt, Seyfollah Bazarjani
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Patent number: 6144231Abstract: A dynamic latching comparator is provided for use with first and second signal input lines. The dynamic latching comparator includes latching circuitry having first and second pull-up devices connected, respectively, between first and second nodes and a high voltage source and first and second pull-down devices connected, respectively, between the first and second nodes and a ground. The first and second pull-down devices have gates connected, respectively, to the first and second input lines. A gate of the first pull-up device is cross-coupled to the second node. A gate of the second pull-up device is cross-coupled to the first node. The dynamic latching comparator also includes differential amplifier circuitry having third and fourth pull-down devices connected, respectively, between the first and second nodes and the ground. A gate of the third pull-down device is cross-coupled to the second node. A gate of the fourth pull-down device cross-coupled to the first node.Type: GrantFiled: November 23, 1998Date of Patent: November 7, 2000Inventor: Jeremy Mark Goldblatt