Patents by Inventor Jeremy P. Schreiber

Jeremy P. Schreiber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power-gated retention flops
    Patent number: 8381163
    Abstract: A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: February 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeremy P. Schreiber, Aaron Grenat
  • POWER-GATED RETENTION FLOPS
    Publication number: 20120131526
    Abstract: A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Inventors: Jeremy P. Schreiber, Aaron Grenat