Abstract: Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

Abstract: Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

Abstract: A voltage buffer includes a high impedance input and a low impedance output. In one example, the buffer includes a source-follower FET and load FET, at least one of which has a forward-biased source-body junction. Another example includes a cascade of two source-follower FETs of opposite conductivity types, and corresponding load devices. Another example further reduces the buffer's output impedance by using a diode-connected load device. The voltage buffer is effectively referenced to a first power supply and effectively isolated from a second power supply. Therefore, it tracks variations in the first power supply voltage, but does not track variations in the second power supply voltage.

Abstract: A voltage buffer includes a high impedance input and a low impedance output. In one example, the buffer includes a source-follower FET and load FET, at least one of which has a forward-biased source-body junction. Another example includes a cascade of two source-follower FETs of opposite conductivity types, and corresponding load devices. Another example further reduces the buffer's output impedance by using a diode-connected load device. The voltage buffer is effectively referenced to a first power supply and effectively isolated from a second power supply. Therefore, it tracks variations in the first power supply voltage, but does not track variations in the second power supply voltage.