Abstract: Systems and methods can support a prize-based digital advertising system. The system can receive advertising material associated with an offering from an advertiser. The advertising materials may be presented on one or more public display devices associated with a client system. Game play opportunities associated with the advertising material and the offering may be presented on the one or more public display devices. The client system can support game play by a user at the one or more public display devices. The user may be provided with a discount towards purchasing the offering. The user may also be provided the offering as a prize in response to achieving specified game play performance such as winning or placing within a tournament.

Abstract: Systems and methods can support a prize-based digital advertising system. The system can receive advertising material associated with an offering from an advertiser. The advertising materials may be presented on one or more public display devices associated with a client system. Game play opportunities associated with the advertising material and the offering may be presented on the one or more public display devices. The client system can support game play by a user at the one or more public display devices. The user may be provided with a discount towards purchasing the offering. The user may also be provided the offering as a prize in response to achieving specified game play performance such as winning or placing within a tournament.

Abstract: Systems, methods and devices are disclosed that provided for providing remote video feedback. The disclosure herein includes a transmitting computing device that is configured to produce an image frame encoded with metadata and to transmit the encoded image frame over a network to a remote display device. The remote display device includes a viewing screen contained in a chassis with bevel. The viewing screen includes an information validation pixel with the chassis extending over and covering the image validation pixel. The chassis also includes a photo sensor positioned on the under side of the bezel so as to be in operational view of the image validation pixel. The system also includes a sensor electronics module that is configured to detect the metadata when the metadata is displayed by the information content pixel and is received by the photo sensor. The sensor electronics module also generates image frame feedback information based upon the detecting.

Abstract: Systems, methods and devices are disclosed that provided for providing remote video feedback. The disclosure herein includes a transmitting computing device that is configured to produce an image frame encoded with metadata and to transmit the encoded image frame over a network to a remote display device. The remote display device includes a viewing screen contained in a chassis with bevel. The viewing screen includes an information validation pixel with the chassis extending over and covering the image validation pixel. The chassis also includes a photo sensor positioned on the under side of the bezel so as to be in operational view of the image validation pixel. The system also includes a sensor electronics module that is configured to detect the metadata when the metadata is displayed by the information content pixel and is received by the photo sensor. The sensor electronics module also generates image frame feedback information based upon the detecting.

Abstract: An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Abstract: A method for detecting a single event functional interrupt for an electronic circuit is provided. The method involves periodically generating a refresh signal for the electronic circuit, and generating a single event functional interrupt indicator signal in the electronic circuit that is responsive to the refresh signal. The method also involves monitoring the single event functional interrupt indicator signal for a state that indicates a failed refresh attempt.

Abstract: An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.

Abstract: An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on a chip, and network on a chip designs.

Abstract: Methods and systems for assembling spacecraft in space are provided. A modular spacecraft comprises a plurality of spacecraft modules, wherein each spacecraft module includes one or more of bonding posts and receiving plates mounted to an exterior surface each spacecraft module, wherein the one or more bonding posts and receiving plates are adapted to form one or more of, an electro-weld bond and an adhesive bond, with the one or more receiving plates.

Abstract: An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Abstract: A reconfigurable computer is disclosed. The computer includes a controller and at least one reconfigurable processing element communicatively coupled to the controller. The controller is operable to read at least a first portion of a respective configuration of each of the plurality of reconfigurable processing elements and refresh at least a portion of the respective configuration of the reconfigurable processing element if the first portion of the configuration of the reconfigurable processing element has changed since the first portion was last checked.

Abstract: A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload data is written to the multi-port communication device and a second port at which at least a portion raw payload data written to the multi-port communication device is read by the reconfigurable processing element. The reconfigurable computer further includes a controller coupled to the reconfigurable processing element. The controller applies the configuration to the reconfigurable processing element and wherein the controller performs at least one single event upset mitigation operation.

Abstract: An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on a chip, and network on a chip designs.

Abstract: System and methods for satellite payload application development are provided. A method for developing embedded processing systems comprises selecting a hardware layer configuration; and developing an interfacing software stack providing services from one or more of an infrastructure services layer, a bus abstraction layer, a device abstraction layer, and a peripheral device driver layer through one or more standard function calls.

Abstract: A method for detecting a single event functional interrupt for an electronic circuit is provided. The method involves periodically generating a refresh signal for the electronic circuit, and generating a single event functional interrupt indicator signal in the electronic circuit that is responsive to the refresh signal. The method also involves monitoring the single event functional interrupt indicator signal for a state that indicates a failed refresh attempt.

Abstract: Methods and systems for assembling spacecraft in space are provided. A modular spacecraft comprises a plurality of spacecraft modules, wherein each spacecraft module includes one or more of bonding posts and receiving plates mounted to an exterior surface each spacecraft module, wherein the one or more bonding posts and receiving plates are adapted to form one or more of, an electro-weld bond and an adhesive bond, with the one or more receiving plates.

Abstract: Methods and systems for processing digital video data are provided. In one embodiment, a method comprises capturing one or more video images and generating serial digital video signals of the one or more video images. The method further comprises filtering one or more of color, sound, and control symbols from the serial digital video signals. The method further comprises storing the serial digital video signals as a memory mapped image in one or more memories; performing one or more image enhancement operations on the memory mapped image, including one or more of digital filtering, edge detection, image cropping and image magnification; and generating second serial digital video signals of the transmitted memory mapped images by one or more of, restoring control symbols, inserting blank color data samples, inserting blank sound data samples.

Abstract: A method and system for adapting fault tolerant computing. The method includes the steps of measuring an environmental condition representative of an environment. An on-board processing system's sensitivity to the measured environmental condition is measured. It is determined whether to reconfigure a fault tolerance of the on-board processing system based in part on the measured environmental condition. The fault tolerance of the on-board processing system may be reconfigured based in part on the measured environmental condition.

Abstract: An improved system and method for dynamically optimizing the performance and reliability of redundant processing systems (e.g., for use in space applications) are disclosed. As one example, a Field Programmable Gate Array (FPGA) that includes a plurality of processors is disclosed. Based on mission specific modes or environmental conditions, the processing system can dynamically and safely transition between the high performance of, for example, a general purpose, quad Symmetric Multiprocessor (SMP) and the high reliability of a redundant set of processors (e.g., Triple Modular Redundancy system). This architecture allows the use of a single FPGA with multiple processors to take advantage of the maximum processing throughput available when sufficient mission conditions are met, and can also safely transition to a lower throughput, high reliability mode when needed.

Abstract: Systems and methods for reconfigurable wireless interconnects for data communication are provided. A computer system comprises a plurality of processing elements and one or more reconfigurable wireless interconnects. Each processing element is adapted to communicate data to at least on other processing element through the one or more reconfigurable wireless interconnects.