Patents by Inventor Jeremy Rashid

Jeremy Rashid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8432030
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 30, 2013
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C Mark Johnson, Cyril Buttay, Jeremy Rashid, Florin Udrea
  • Patent number: 8274086
    Abstract: A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: September 25, 2012
    Assignees: DENSO CORPORATION, University of Cambridge
    Inventors: Rajesh Kumar Malhan, Yuuichi Takeuchi, Jeremy Rashid
  • Publication number: 20110254177
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Applicants: DENSO CORPORATION, The University of Sheffield, University of Cambridge
    Inventors: Rajesh Kumar MALHAN, C Mark JOHNSON, Cyril BUTTAY, Jeremy RASHID, Florin UDREA
  • Patent number: 7999369
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: August 16, 2011
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C. Mark Johnson, Cyril Buttay, Jeremy Rashid, Florin Udrea
  • Publication number: 20100025693
    Abstract: A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Applicants: DENSO CORPORATION, University of Cambridge
    Inventors: Rajesh Kumar Malhan, Yuuichi Takeuchi, Jeremy Rashid
  • Patent number: 7557434
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: July 7, 2009
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C. Mark Johnson, Jeremy Rashid
  • Publication number: 20080054425
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 6, 2008
    Applicants: DENSO CORPORATION, UNIVERSITY OF CAMBRIDGE, THE UNIVERSITY OF SHEFFIELD
    Inventors: Rajesh Kumar Malhan, C. Mark Johnson, Jeremy Rashid
  • Publication number: 20080054439
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 6, 2008
    Applicants: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C. Mark Johnson, Cyril Buttay, Jeremy Rashid, Florin Udrea