Abstract: The invention relates to a method of manufacturing high durability timber product, the method comprising: a) selecting a durable substrate timber; b) selecting a veneer of high-performance timber; and c) gluing the veneer of high-performance timber to the face of the durable substrate 5 timber, wherein the resulting manufactured high durability timber product is suitable for long-term use in exterior applications at a lower cost than that of the same thickness timber product if made of high-performance timber alone.

Abstract: The invention relates to methods to thermally treat wood (e.g., flat-grain timber) to produce wood with enhanced color and/or weathering properties.

Abstract: The invention relates to methods to thermally treat wood (e.g., flat-grain timber) to produce wood with enhanced color and/or weathering properties.

Abstract: The invention relates to methods to thermally treat wood (e.g., flat-grain timber) to produce wood with enhanced color and/or weathering properties.

Abstract: The invention relates to methods to thermally treat wood (e.g., flat-grain timber) to produce wood with enhanced color and/or weathering properties.

Abstract: A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: A metal container or component part of a metal container (e.g. a can end or sidewall of a can body) has an aperture defined by a cut edge about the periphery of the aperture, with a cover element sealed to the outward-facing surface of the can end so as to extend over and cover the aperture. A film of lacquer is directly applied (without the presence of an intermediate primer layer) to the inward-facing of the container/component part so as to coat the entirety of the cut edge and all or part of the inward-facing surfaces of both the can end and that part of the cover element located radially inward of the cut edge, thereby inhibiting corrosion of the cut edge. The invention is particularly suitable for can ends. The invention also relates to a method of making a can end to the invention.

Abstract: An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.

Abstract: A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant memory element and compare logic for determining whether an address of a failing memory element is stored in the register.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.

Abstract: A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant memory element and compare logic for determining whether an address of a failing memory element is stored in the register.

Abstract: A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14).

Abstract: A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.

Abstract: A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

Abstract: A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.