Patents by Inventor Jeremy Rutledge Levitt
Jeremy Rutledge Levitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9684760Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: January 12, 2016Date of Patent: June 20, 2017Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20160125122Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: ApplicationFiled: January 12, 2016Publication date: May 5, 2016Inventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 9262557Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: April 8, 2013Date of Patent: February 16, 2016Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20130239084Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: ApplicationFiled: April 8, 2013Publication date: September 12, 2013Applicant: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 8418121Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: February 14, 2011Date of Patent: April 9, 2013Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 8060847Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.Type: GrantFiled: December 23, 2008Date of Patent: November 15, 2011Assignee: Mentor Graphics CorporationInventors: James Andrew Garrard Seawright, Jeremy Rutledge Levitt, Christophe Gauthron
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Publication number: 20110138346Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Patent number: 7890897Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: November 13, 2007Date of Patent: February 15, 2011Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20090144684Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.Type: ApplicationFiled: December 23, 2008Publication date: June 4, 2009Applicant: Mentor Graphics Corp.Inventors: James Andrew Garrard Seawright, Jeremy Rutledge Levitt, Christophe Gauthron
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Patent number: 7487483Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.Type: GrantFiled: May 18, 2006Date of Patent: February 3, 2009Inventors: James Andrew Garrard Seawright, Jeremy Rutledge Levitt, Christophe Gauthron
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Patent number: 7318205Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: December 6, 2004Date of Patent: January 8, 2008Inventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan
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Publication number: 20070271536Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Applicant: Mentor Graphics Corp.Inventors: James Andrew Garrard Seawright, Jeremy Rutledge Levitt, Christophe Gauthron
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Patent number: 6848088Abstract: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicated that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.Type: GrantFiled: June 17, 2002Date of Patent: January 25, 2005Assignee: Mentor Graphics CorporationInventors: Jeremy Rutledge Levitt, Christophe Gauthron, Chian-Min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan