Abstract: A digital processor for two's complement computations incorporates an array of multiplier cells each having the one-bit gated full adder logic function. The array has nearest-neighbour connections containing clock-activated latches for bit propagation. On each clock cycle, the cells receive input data, carry and cumulative sum bits. Each cell adds the carry and cumulative sum bits to the product of the data bit and a respective digit associated with the relevant cell. Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell includes logic gates responsive to the sign and level bits, and carry a feedback latch and multiplier combination responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit.

Abstract: A digital data processor for matrix-vector multiplication is provided, and comprises a systolic array of bit level, synchronously clock activated processing cells each connected to its row and column neighbours. On each clock cycle, each cell mutiplies an input bit of a respective vector coefficient by a respective matrix coefficient equal to +1, -1 or 0, and adds it to cumulative sum and carry input bits. Input vector coefficient bits pass along respective array rows through one cell per clock cycle, Contributions to matrix-vector product bits are accumulated in array columns. Input to and output from the array is bit-serial, word parallel, least significant bit leading, and temporally skewed. Transforms such as the discrete Fourier transform may be implemented by a two-channel device, in which each channel contains two processors of the invention with an intervening bit serial multiplier. Processors of the invention may be replicated to implement multiplication by larger matrices.