Abstract: Methods and systems for preserving dynamic random access memory content in response to a hung processor condition are disclosed. In order to preserve dynamic random access memory content, a first watchdog timer is initiated and strobed at a predetermined time interval less than its timeout value. If a hung processor condition occurs and the strobing of the first watchdog timer fails, the first watchdog timer generates a non-maskable interrupt to the processor. The non-maskable interrupt triggers the processor to execute an interrupt service routine. If the processor is able to execute the interrupt service routine, the interrupt service routine controls the processor to perform a selective system reset and preserve dynamic random access memory contents. If the processor is not capable of executing the interrupt service routine, a board reset occurs and dynamic random access memory contents are cleared.

Abstract: A programmable logic device (PLD) in a microprocessor system is programmed with minimal load on system resources. A microprocessor reads programming data from a first memory using a parallel bussed interface and writes the programming data to a programming hardware assist engine using the parallel bussed interface. The programming hardware assist engine directs a portion of the programming data to a specified serial interface signal, and outputs a serial bit stream from the programming hardware assist engine to a serial programming interface of the PLD using the specified serial interface signal.

Abstract: Methods and systems for preserving dynamic random access memory content in response to a hung processor condition are disclosed. In order to preserve dynamic random access memory content, a first watchdog timer is initiated and strobed at a predetermined time interval less than its timeout value. If a hung processor condition occurs and the strobing of the first watchdog timer fails, the first watchdog timer generates a non-maskable interrupt to the processor. The non-maskable interrupt triggers the processor to execute an interrupt service routine. If the processor is able to execute the interrupt service routine, the interrupt service routine controls the processor to perform a selective system reset and preserve dynamic random access memory contents. If the processor is not capable of executing the interrupt service routine, a board reset occurs and dynamic random access memory contents are cleared.