Abstract: Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.

Abstract: Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.

Abstract: Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing.

Abstract: Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.

Abstract: A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.

Abstract: Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing.

Abstract: Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.

Abstract: A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein.

Abstract: Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist.

Abstract: A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein.

Abstract: A technique for implementing an engineering change order (ECO) includes comparing a first hardware description language (HDL) design with a second HDL design. In this case, the second HDL design corresponds to the first HDL design with at least one implemented ECO. The technique identifies differences in latch points, primary inputs, and primary outputs between the first and second HDL designs. The second HDL design is converted to a non-optimized netlist. Logical cones (cones of logic) that feed the latch points, the primary inputs, and the primary outputs are extracted from the non-optimized netlist. Based on the extracted logical cones and the non-optimized netlist, a physical implementation of the second HDL design is synthesized.

Abstract: A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.