Abstract: A charge pump arrangement for a phase-locked-loop has a current source circuit (60) which provides charging current to the phase locked loop, and a current sink circuit (90) which depletes charging current from the phase locked loop. The current source circuit (60) and the current sink circuit (90) have slew rates which have a predetermined relationship. In this way, the charge pump causes substantially no non-linear charge injection in the phase-locked-loop. Cascoded current mirrors (75, 85) are utilised to provide a high voltage with thin gate oxide technology. The arrangement has a relatively small die size. Since bias currents of the arrangement are mirrored according to the output current required, improved transient times are produced, leading to reduced phase noise.

Abstract: A charge pump arrangement for a phase-locked-loop has a current source circuit (60) which provides charging current to the phase locked loop, and a current sink circuit (90) which depletes charging current from the phase locked loop. The current source circuit (60) and the current sink circuit (90) have slew rates which have a predetermined relationship. In this way, the charge pump causes substantially no non-linear charge injection in the phase-locked-loop. Cascoded current mirrors (75, 85) are utilised to provide a high voltage with thin gate oxide technology. The arrangement has a relatively small die size. Since bias currents of the arrangement are mirrored according to the output current required, improved transient times are produced, leading to reduced phase noise.

Abstract: A memory circuit (24) limits the threshold voltage distribution for either programming or erasing a memory cell (40A) in a non-volatile memory array (34). A data latch (90) provides a current (I.sub.REF) to the memory cell (40A) that increases in current as the operating temperature of the memory cells (40A, 40B) increases. Current generated by the data latch (90) increases when the processing parameters cause a greater conductivity of the transistors in the memory cell (40A) and the current decreases when the processing parameters cause a lesser conductivity of the transistors in the memory cell (40A), thus allowing narrower limits on the distribution of the program and erase threshold voltages.

Abstract: A charge pump (102) and method of charge pumping a low voltage (V.sub.DD)) to generate a higher voltage (V.sub.PP). A primary pump (160, 179, 180) receives complementary clock signals (CLK1, CLK2) that control charging and transfer cycles of the charge pump. During the charging cycle, a capacitor (150) stores a charge developed from the low voltage. On the transfer cycle, the charge is transferred to an output (138, 177, 178) through a switching transistor (152) disposed in a well region (202) to develop the higher voltage. A secondary pump (162, 187, 188) charge pumps the output voltage to generate a more positive bias voltage for biasing the well region to disable a parasitic PNP transistor of the switching transistor.

Abstract: A programming method for a floating gate memory circuit (100) includes a block erase (step 81) in which a first programming signal is applied to memory cells of a selected block of the memory to store a first value of charge in the memory cells of the block. Data is programmed by applying a second programming signal to a first memory cell to store a second value in the first memory cell (step 83). A third programming signal is applied to a second memory cell to write a correction charge that compensates for a change in the first value of charge induced by the second programming signal (step 84).

Abstract: A current limiting circuit (70) controls the leakage current of a memory circuit (24) of a portable wireless device (10) while operating in a standby mode. A first semiconductor well (64) isolates the memory circuit (24) that is disposed in a second semiconductor well (66) from a substrate (62). In the standby mode the current limiting circuit (70) is switched to a non-conduction mode that limits the leakage currents of a diode formed by the first semiconductor well (66) with the second semiconductor well (64) and a diode formed by the second semiconductor well (64) with the substrate (62).

Abstract: A circuit and method modify data stored in a storage element (30) of a memory circuit (110) when high voltages used for such modification exceed transistor breakdowns. A charge pump (302) produces a pumped voltage (V.sub.P1) for modifying the data. A monitor circuit (304) produces an enable signal (V.sub.PEN) to activate other power supply voltages when the pumped voltage reaches a predetermined voltage level for allowing the data to be modified. A routing circuit (832) selects between the pumped voltage and a first voltage (V.sub.DD) in response to a first control signal (HVENABLEP) to produce a selected voltage. A switching circuit (802-808) passes the selected voltage to the storage element (30) to modify the data when the first supply voltage is selected by the routing circuit.

Abstract: A memory circuit (24) includes a sense amp circuit (30) that uses multiplexers (86) in a column mux (32) for pre-charging only selected bitlines in order to limit the current during a read operation of the FLASH memory circuit (24). The sense amp circuit (30) provides the bitline with a pre-charge voltage that is set by a current reference (68) that is substantially supply independent. In the read mode the sense amp circuit (30) responds to either a voltage on the bitline that is lowered from the pre-charge voltage value by a selected programmed memory cell (40) or by a voltage that remains at the pre-charged voltage value for an unprogrammed memory cell.