Abstract: Materials with etch selectivity with respect to one another and one or more additional etch-stop layers are used in a Josephson junction structure to allow for integration with a Josephson junction with supporting structures such as resistors. Selective etch processes compatible with high volume manufacturing are used to pattern various layers of the Josephson junction structure to provide a Josephson junction, which is electrically coupled to a support structure.

Abstract: Low VOC thermosetting polyester acrylic resins are made by esterification of unsaturated epoxide such as glycidyl methacrylate, and a polyacid which is the half-ester formed by reacting an acid or its anhydride with a polyol is disclosed. The obtained low viscosity resin is useful for making a low or zero VOC gel coat with excellent hydrolytic and weather resistance.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: Low VOC thermosetting polyester acrylic resins are made by esterification of unsaturated epoxide such as glycidyl methacrylate, and a polyacid which is the half-ester formed by reacting an acid or its anhydride with a polyol is disclosed. The obtained low viscosity resin is useful for making a low or zero VOC gel coat with excellent hydrolytic and weather resistance.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract: Embodiments of the present invention are directed to methods and systems for processing and/or validating data using a graphical user interface of a computer system. Embodiments may include arranging a plurality of nodes in a graph, where each node represents at least one processing step for processing data by a processor and wherein at least one of the plurality of nodes comprise at least one data retrieval node for retrieving data for validation. The method may also include establishing at least one output from substantially all of the plurality of nodes, except for the at least one data retrieval node, establishing at least one input to each of the plurality of nodes, configuring one or more parameters of each node, and linking at least one output of each of substantially all of the plurality of nodes to an input of another node, where each link representing a data flow.

Abstract: Systems and methods for determining discrepancies of a communication system including at least one data source, at least one data parser and/or data adaptor, at least one data loader and/or data abstractor, at least one database abstraction, at least one data store, an invoice management module, a revenue and cost management module, an intercarrier traffic management module, a secondary user-interface table and a user interface.