Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.

Abstract: An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.

Abstract: Systems or methods of the present disclosure may provide a library including multiple regional bits streams that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more regional bitstreams and stitched to form a larger combined bitstream to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The combined bitstreams may be loaded into all or a portion of the integrated circuit device to realize the design. Additionally or alternatively, the integrated circuit device may include a hardened networks-on-chip to improve data routing within the combined bitstream.

Abstract: Systems or methods of the present disclosure may provide a library including multiple personas that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more personas to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The personas may be loaded into one or more regions of the integrated circuit device to realize the design. That is, the design may be realized by one persona may be implemented across multiple regions, one region may be configured by multiple personas, one persona configuring one region, or any combination thereof. Additionally or alternatively, the integrated circuit device may include networks-on-chip to improve data routing between the regions.

Abstract: Systems or methods of the present disclosure may provide a compilation design method that uses cloud computing resources and/or distributed computing resources to compile initial user designs. The initial user design for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic. The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs.

Abstract: Systems or methods of the present disclosure may provide a programmable fabric including programmable logic. The programmable logic may include memory, a network-on-chip (NOC), and at least one micro NOC formed with hardened resources in the programmable fabric. Further, the at least one micro NOC may be communicatively coupled to the NOC and to the programmable logic. Additionally, the at least one micro NOC may selectively route data between the NOC and the programmable logic.

Abstract: An integrated circuit device includes a programmable fabric that has a plurality of memory blocks. The integrated circuit device also includes a network-on-chip (NOC) located on a shoreline of the programmable fabric and at least one micro NOC formed with hardened resources in the programmable fabric. The at least one micro NOC is communicatively coupled to the NOC and to at least one memory block of the plurality of memory blocks. Additionally, the at least one micro NOC is configurable to route data between the NOC and the at least one memory block.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

Abstract: An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

Abstract: A method for producing highly reactive olefin polymers wherein at least 50 mol. % of the polymer chains have terminal double bonds, from an impurity-containing isobutylene or a mixed C4 hydrocarbyl feedstock containing isobutylene in which the water content of the feedstock is controlled to be at least equal to the content of polar impurities in the feedstock, and less than the concentration at which the water causes a decrease in vinylidene end-group selectivity.

Abstract: A method for producing highly reactive olefin polymers wherein at least 50 mol. % of the polymer chains have terminal double bonds, from an impurity-containing isobutylene or a mixed C4 hydrocarbyl feedstock containing isobutylene in which the water content of the feedstock is controlled to be at least equal to the content of polar impurities in the feedstock, and less than the concentration at which the water causes a decrease in vinylidene end-group selectivity.

Abstract: A method for producing highly reactive olefin polymers wherein at least 50 mol. % of the polymer chains have terminal double bonds, from an isobutylene or a mixed C4 hydrocarbyl feedstock containing isobutylene. To achieve a viable process, water is added to the catalyst stream or the feedstock in the overall range of 0.05 mM to less than 5 mM per liter of feedstock.

Abstract: One aspect provides a loop based social networking site. An embodiment provides for loops, a loop comprising a list or group of registered users bound together as an electronic group, and provides a mechanism of pushing communications to members of a loop. As such, on joining as a member of a particular loop, the loop member will have events of the loop automatically pushed to the user's personal or individual loop site, including in some cases automatic addition of the event to the personal calendar of the loop member. In this way, a loop can ensure that each member has received particular communications. Each loop member consents to accepting loop information/communications by virtue of joining the loop. Other aspects are described and claimed.