Abstract: The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being the same as the write address.

Abstract: One example includes a memory circuit. The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being equal to the write address.

Abstract: One embodiment describes a quantum memory system. The system includes an array controller that comprises a plurality of flux pumps configured to provide write currents in a write operation and read currents in a read operation with respect to a plurality of quantum memory cells, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

Abstract: One embodiment describes a quantum memory system. The system includes an array controller that comprises a plurality of flux pumps configured to provide write currents in a write operation and read currents in a read operation with respect to a plurality of quantum memory cells, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

Abstract: One embodiment describes a quantum memory system. The system includes a plurality of quantum memory cells arranged in an array of rows and columns. Each of the plurality of quantum memory cells can be configured to store a binary logic state in response to write currents in a write operation and configured to provide an indication of the binary logic state in response to read currents in a read operation. The system also includes an array controller comprising a plurality of flux pumps configured to provide the write currents and the read currents with respect to the rows and columns. The array controller can be configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

Abstract: An apparatus for servicing connections in a telecommunications network comprises N ports in communication with the connections through the network. Each port supporting a plurality of virtual links, and each virtual link supporting a plurality of rate groups. The apparatus comprises a processor for providing service to the connections. The apparatus comprises an associative array that stores timestamps of the virtual links and the rate groups. The apparatus comprises a scheduler which chooses which virtual link and rate group is to receive service from the processor as a function of a timestamp. An apparatus for servicing connections in a telecommunications network. The apparatus comprises N ports in communication with the connections through the network. Each port supporting a plurality of virtual links, and each virtual link supporting a plurality of rate groups. The apparatus comprises a processor for providing service to the connections.

Abstract: An apparatus for transferring data in a telecommunications network. The apparatus includes a memory in which a packet memory length is stored. The apparatus includes a mechanism for determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network. The apparatus includes a mechanism for sending the packet having the link length to the network. A method for transferring data in a telecommunications network. The method includes the steps of storing in a memory a memory length of a packet. There is the step of determining a link length for the packet that will be sent into the network based on the memory length and at least one parameter, where the link length correctly corresponds to the packet's physical line bandwidth usage in the network There is the step of sending the packet having the link length to the network.

Abstract: A multiple key self-sorting table. The table includes a plurality of intelligent self-sorting modules. Each module of the plurality of modules having an entry with at least one value. Each module making a decision to perform one of a plurality of acts, and preferably four acts, when there is an addition or deletion of an entry to the table; it holds its current value, stores a new entry, takes an entry from its immediately adjacent module with a higher value or takes an entry from its immediately adjacent module with a lower value; and performing the decision. A method for sorting a table.