Abstract: A computer-implemented method is disclosed for adjusting impedance of a differential via pair in an electrical circuit layout. A differential via pair having an odd mode characteristic impedance needing adjustment is identified in a circuit design database. A region is established around the differential via pair in which circuit elements may be modified to adjust the odd mode characteristic impedance of the differential via pair. At least one of the circuit elements in the electrical circuit layout in the established region is adjusted until the odd mode characteristic impedance is closer to a desired odd mode characteristic impedance value.

Abstract: A computer-implemented method is disclosed for adjusting impedance. A list of differential line pairs in a circuit design database is searched through for a target differential line pair, where the target differential line pair is flagged as having an incorrect characteristic impedance. A position in a circuit layout described in said circuit design database of at least one line in the differential line pair is adjusted to correct the characteristic impedance.

Abstract: A computer-implemented method is disclosed for verifying signal via impedance. Properties of a signal via and of any other vias within a given distance of the signal via are read from a circuit design database. A target characteristic impedance value for the signal via is obtained. A characteristic impedance of the signal via is calculated based on the other vias. The signal via is flagged as having an incorrect characteristic impedance if the calculated characteristic impedance does not match the target characteristic impedance value.

Abstract: A computer-implemented method for adjusting impedance is disclosed. A desired impedance value for a signal line in an electrical circuit layout is read, and the signal line is identified in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance adjustment for the signal line. The impedance adjustment is performed by adjusting at least one of the circuit elements in the window to bring an impedance of the signal line nearer the desired impedance value.

Abstract: A computer-implemented method is disclosed for verifying differential line pair impedance. Properties for a differential line pair segment are read from a circuit design database. Properties of neighboring traces are also from the circuit design database, with the neighboring traces being within a given distance of the differential line pair segment. A modal characteristic impedance of the differential line pair segment is calculated based on the neighboring traces. The differential line pair segment is flagged as having an improper impedance value if the calculated modal characteristic impedance differs from a desired modal characteristic impedance.

Abstract: A computer-implemented method is disclosed for verifying impedance in a differential via pair. A target differential via pair is identified in a design database. A desired modal characteristic impedance for the target differential via pair is obtained. A two-dimensional window is established around the differential via pair in which neighboring vias will be included in a modal characteristic impedance calculation for the target differential via pair. A modal characteristic impedance for the target differential via pair is calculated based at least in part on the neighboring vias in the two-dimensional window. The target differential via pair is flagged if the calculated modal characteristic impedance does not match the desired modal characteristic impedance.

Abstract: A computer-implemented method for verifying impedance of a signal line in an electrical circuit layout includes reading a desired impedance value for a signal line and identifying the signal line in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance calculation for the signal line. The impedance of the signal line is calculated based on the circuit elements inside the window. The signal line is flagged if the calculated impedance differs from the desired impedance value.

Abstract: A computer-implemented method for adjusting signal via impedance includes identifying a signal via in a circuit design database. The signal via is flagged as having an impedance error. A window is established around the signal via, with the window lying on a single layer. Only vias in the window may be adjusted to minimize the impedance error. At least one via in the window is adjusted to minimize said impedance error.