Patents by Inventor Jermmy J. M. Wang

Jermmy J. M. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5889361
    Abstract: A cold cathode field emission device is described. A key feature of its design is that groups of microtips share a single conductive disk with a reliable ballast resistor being interposed between each of these conductive disks and the cathode conductor. Additionally, a resistor, rather than a conductor, is used to connect the gate conductive disk to the gate electrode. The latter is arranged so as not to overlap with the cathode electrode. The cathode and gate conductive disks ensure that the ballast resistance associated with each microtip is essentially the same.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: March 30, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Wen Chun Wang, Jermmy J. M. Wang, Tzung-Zu Yang
  • Patent number: 5791961
    Abstract: A cold cathode field emission device is described. A key feature of its design is that groups of microtips share a single conductive disk with a reliable ballast resistor being interposed between each of these conductive disks and the cathode conductor. Additionally, a resistor, rather than a conductor, is used to connect the gate conductive disk to the gate electrode. The latter is arranged so as not to overlap with the cathode electrode. The cathode and gate conductive disks ensure that the ballast resistance asociated with each microtip is essentially the same.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: August 11, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Wen Chun Wang, Jermmy J. M. Wang, Tzung-Zu Yang
  • Patent number: 5656525
    Abstract: A new method for forming an array of high aspect ratio field emitter for flat panel Field Emission Displays (FEDs) was accomplished. The method involves forming on an insulated substrate an array of parallel cathodes and then depositing a dielectric layer and forming a array of parallel gate electrodes essentially orthogonal to the array of cathode electrodes. Opening are then made in the upper gate electrodes and dielectric layer over the lower cathode electrodes. The field emitters with high aspect-ratios are then formed on the cathode by depositing an emitter material, such as molybdenum, in the opening while heating the substrate to high temperatures. The emitter material is removed elsewhere on the substrate by utilizing a release layer and thereby completing the gated field emitter. This high temperature method results in high aspect-ratio gated emitters that allow the inter-electrode dielectric layer to be increased and thereby improving the circuit performance.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: August 12, 1997
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Yuan Lin, Peng Chao-Chi, Kyan-Lun Chang, Jermmy J. M. Wang