Abstract: A radio-frequency integrated circuit can be protected by a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of an amplifier and a related controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.

Abstract: Amplifier having electrostatic discharge and surge protection circuit. In some embodiments, a radio-frequency integrated circuit can include an amplifier, a controller configured to control operation of the amplifier, and a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of the amplifier and the controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.

Abstract: A transistor can include a source and a drain with each implemented in a first type active region, a gate implemented relative to the source and the drain, and a body implemented in the first type active region and substantially covered by the gate. The transistor can further include a body tie implemented in a second type active region and including a connecting portion substantially covered by the gate and engaging the body. The first and second active regions can be dimensioned to provide a gap therebetween on each side of the gate.

Abstract: Amplifier having electrostatic discharge and surge protection circuit. In some embodiments, a radio-frequency integrated circuit can include an amplifier, a controller configured to control operation of the amplifier, and a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of the amplifier and the controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.

Abstract: Concurrent electrostatic discharge and surge protection clamps in power amplifiers. In some embodiments, a semiconductor die can include a semiconductor substrate and an integrated circuit implemented on the semiconductor substrate. The integrated circuit can include a power amplifier and a controller. The semiconductor die can further include a clamp circuit implemented on the semiconductor substrate and configured to provide electrostatic discharge protection and surge protection for at least some of the integrated circuit.

Abstract: Concurrent electrostatic discharge and surge protection clamps in power amplifiers. In some embodiments, a semiconductor die can include a semiconductor substrate and an integrated circuit implemented on the semiconductor substrate. The integrated circuit can include a power amplifier and a controller. The semiconductor die can further include a clamp circuit implemented on the semiconductor substrate and configured to provide electrostatic discharge protection and surge protection for at least some of the integrated circuit.

Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.

Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.