Patents by Inventor Jerng-Cherng Fan

Jerng-Cherng Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for dispatching multiple interrupt requests simultaneously
    Patent number: 5918057
    Abstract: An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: June 29, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Chich Chou, Jerng-Cherng Fan, Tsahn-Yih Chang, Po-Chuan Kang
  • Method and apparatus for selecting a nonblocked interrupt request
    Patent number: 5905897
    Abstract: An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: May 18, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Chich Chou, Jerng-Cherng Fan, Won-Yih Lin, Ching-Chin Huang