Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Discharge circuits, devices and methods. In some embodiments, a MEMS device can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS device can further include a discharge circuit implemented relative to the electromechanical assembly. The discharge circuit can be configured to provide a preferred arcing path during a discharge condition affecting the electromechanical assembly. The MEMS device can be, for example, a switching device, a capacitance device, a gyroscope sensor device, an accelerometer device, a surface acoustic wave (SAW) device, or a bulk acoustic wave (BAW) device. The discharge circuit can include a spark gap assembly having one or more spark gap elements configured to facilitate the preferred arcing path.

Abstract: Circuits, systems, and methods to compensate for non-linearities associated with a switching circuit are discussed herein. For example, a switch circuit can include a switch arm and a linearizer arm. The switch arm can have a first transistor connected between an input node and an output node. The switch arm can be configured to receive a radio-frequency signal. The linearizer arm can have a second transistor connected to at least one of a gate or a body of the first transistor. The linearizer arm can be configured to compensate a non-linearity effect generated by the switch arm.

Abstract: Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: A method for fabricating a radio-frequency device involves providing a substrate structure including a silicon handle wafer, an oxide layer formed on the silicon handle wafer, and an active silicon layer disposed on the oxide layer.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: pHEMT-based switch circuits, devices including same, and methods of improving the linearity thereof. In one example, an antenna switch module includes a pHEMT switching circuit connected in series between an input signal terminal and a load terminal, the pHEMT switching circuit including at least one pHEMT configured to produce a first harmonic signal at the load terminal responsive to being driven by an input signal of a fundamental frequency received at the input signal terminal, the first harmonic signal having a first phase, and a gate resistance circuit connected to a gate of the at least one pHEMT and having a resistance value selected to produce a second harmonic signal at the load terminal, the second harmonic signal having a second phase opposite to the first phase.

Abstract: Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

Abstract: Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with a first auxiliary path and the main path in series with a second auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the first auxiliary path. The circuit assembly also includes a third gate bias network connected to the second auxiliary path, the second gate bias network and the third gate bias network configured to improve linearity of the switching function.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.