Abstract: Techniques for hardware based acceleration of synchronous data flow graphs for data-driven multi-core signal processing systems are described. In certain examples, a system includes a processor comprising a processing circuit to perform a task of a synchronous data flow graph, an input memory for the task of the synchronous data flow graph, an output memory for the task of the synchronous data flow graph, and a synchronous data flow manager circuit to store user-visible state for the input memory and the output memory; and a synchronous data flow functional circuit, coupled to the processor, to cause the processing circuit to perform the task based on the user-visible state from the synchronous data flow manager circuit.

Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to: Control a processing circuitry of a computational system including a plurality of processing circuitries to determine if a number of input data token or tokens is available at one or more input buffers of a memory space; and control the processing circuitry to determine if at least a portion of the memory space for a number of output data token or tokens is available at one or more output buffers assigned to the processing circuitry; and control the processing circuitry to execute an iteration of a first task of an application, the application being modelled by a model, if it is determined that the number of input data token or tokens and memory space for the number of output data token or tokens are available.

Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to generate a model modelling a computational system for distributed computation of tasks of an application. The model comprises one or more processor types. The computational system comprises a plurality of processing circuitries, physical memory and a respective memory address space, and one or more interconnects for communication between the plurality of processing circuitries and the physical memory. A processor type includes a processing circuitry identifier, a memory identifier, and an interface identifier.

Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

Abstract: Examples include techniques to reduce power consumption for a distributed computational model mapped onto a multi-processing node system. Examples are described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall consuming compute circuitry based on availability of data to consume. Examples are also described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall producing compute circuitry based on available buffer capacity at a consuming compute circuitry.

Abstract: Techniques are disclosed for a programmable processor array architecture that enables synchronized broadcasting of operation results to register files with the operation results. The architecture advantageously enables writing of operation results of a given operation to multiple destination registers in a single clock cycle for processors with partitioned register files by using common data stationary instruction encoding. This combination brings improved performance by reducing the need for costly copy operations that would otherwise occupy issue slots and thus schedule space while at the same time minimizing code size overhead. The performance gains of broadcasting are especially emphasized in highly parallel and heavily partitioned register file architectures.

Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

Abstract: Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described.

Abstract: Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described.

Abstract: A processor includes a memory and a decompressor. The memory is to store compressed instruction. The decompressor includes logic to receive a request for an instruction in the compressed instructions to be executed by the processor, determine a block in the memory including the requested instruction, and determine a start address of the block in the compressed instructions. The decompressor also includes logic decompress chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions.

Abstract: A memory controller performs DMA operations on arbitrary sized elements unbounded by the word size of the host memory or processor, which performs operations based on an element that represents an atomic data unit such as a pixel. In this manner, a corresponding coding effort is not concerned with computing and locating word boundaries and accommodating unused bits of data conventionally used for accommodating word boundaries on pixel data for video rendering, for example. An element in memory corresponds to a rendered atomic data item, such as a pixel. The controller determines an element precision indicative of a size of the element, and identifies a unit of memory based on a memory location and a packed representation of a plurality of the elements relative to the memory location. The unit has a height and width, defining elements arranged in a grid, and an element position is based on coordinates.

Abstract: A processor includes a memory and a decompressor. The memory is to store compressed instruction. The decompressor includes logic to receive a request for an instruction in the compressed instructions to be executed by the processor, determine a block in the memory including the requested instruction, and determine a start address of the block in the compressed instructions. The decompressor also includes logic decompress chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions.

Abstract: A memory controller performs DMA operations on arbitrary sized elements unbounded by the word size of the host memory or processor, which performs operations based on an element that represents an atomic data unit such as a pixel. In this manner, a corresponding coding effort is not concerned with computing and locating word boundaries and accommodating unused bits of data conventionally used for accommodating word boundaries on pixel data for video rendering, for example. An element in memory corresponds to a rendered atomic data item, such as a pixel. The controller determines an element precision indicative of a size of the element, and identifies a unit of memory based on a memory location and a packed representation of a plurality of the elements relative to the memory location. The unit has a height and width, defining elements arranged in a grid, and an element position is based on coordinates.

Abstract: A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element. The burst generation device (BG) groups a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively.

Abstract: A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element. The burst generation device (BG) groups a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively.

Abstract: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Abstract: In case of time-stationary encoding, every instruction that is part of the processor's instruction-set controls a complete set of operations that have to be executed in a single machine cycle. These operations may be processing several different data items traversing the data pipeline. Time-stationary encoding is often used in application-specific processors, since it saves the overhead of hardware necessary for delaying the control information present in the instructions, at the expense of larger code size. A disadvantage of time-stationary encoding is that is does not support conditional operations. The invention proposes to dynamically control the write back of result data to the register file of the timestationary processor, using control information obtained by the program. By controlling the write back of data at run-time, conditional operations can be implemented by a timestationary processor.

Abstract: Programmable processors are used to transform input data into output data based on program information encoded in instructions. The value of the resulting output data depends, amongst others, on the momentary state of the processor at any given moment in time. This state is composed of temporary data values stored in registers, for example, as well as so-called flags. A disadvantage of the principle of flags, is that they cause side effects in the processor, especially in parallel processors. However, when removing the traditional concept of flags, the remaining problem is the implementation of branching. A processing system according to the invention comprises an execution unit (EX1, EX2), a first register file (RF1, RF2) for storing data, an instruction memory (PM) and a second register file (RF3) for storing a program counter. The execution unit conditionally executes dedicated instructions for writing a value of the program counter into the second register file.

Abstract: Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use of instructions that require large immediate data, while simultaneously maintaining an efficient encoding and decoding of instructions. The processing apparatus comprises a plurality of issue slots (UC0, UC1, UC2, UC3), wherein each issue slot comprises a plurality of functional units (FU20, FU21, FU22). The processing apparatus is arranged for processing data, based on control signals generated from a set of instructions being executed in parallel. The processing apparatus further comprises a dedicated issue slot (UC4) arranged for loading an immediate value (IMV1) in dependence upon a dedicated instruction (IMM).