Patents by Inventor Jeroen Bielen

Jeroen Bielen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948853
    Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: April 2, 2024
    Assignees: QUALCOMM TECHNOLOGIES INCORPORATED, RF360 EUROPE GMBH
    Inventors: Jose Moreira, Markus Valtere, Juergen Portmann, Jeroen Bielen
  • Publication number: 20230090842
    Abstract: A multi-level stacked AW filter package including a first acoustic wave (AW) filter stacked on a second AW filter employs semiconductor fabrication methods and structures, including a metallization layer comprising interconnects to couple a contact surface to the second AW filter. Each AW filter includes an AW filter circuit on a semiconductor substrate. A second substrate disposed on a frame on the substrate protects the AW filter circuit. In a multi-level AW filter package, the second substrate of the first AW filter comprises a glass substrate with a similar expansion rate as the semiconductor substrate. The interconnects coupling the second AW filter to the contact surface are disposed on insulators on the side wall surfaces of the semiconductor substrates of the first AW filter for isolation. In a stacked AW filter package comprising a single AW filter, the interconnects couple the contact surface to the AW filter.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Manuel Hofer, Xavier Perois, Michael Wick, Jeroen Bielen, Stefan Leopold Hatzl, Juergen Portmann
  • Publication number: 20230076844
    Abstract: Semiconductor die module packages with void-defined sections in a metal structure(s) in a package substrate to reduce die-substrate mechanical stress, and related fabrication methods. To reduce die-substrate mechanical stress between the package substrate and a die(s) of the die module package, void-defined sections are formed in a metal structure(s) in a metallization layer(s) of the package substrate. The void-defined sections are formed from one or more cutouts of a metal material of the metal structure in a defined area to reduce stiffness, which also has the effect of reducing the effective coefficient of thermal. expansion (CTE) of the package substrate. The metal material remaining between the metal cutouts in a void-defined section form metal interconnects. Die interconnects can couple a die directly to the metal interconnects in the void-defined sections in the metal structure to reduce mechanical stress between the die and die interconnects to the package substrate.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Andreas Detlefsen, Jeroen Bielen
  • Publication number: 20220359337
    Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer. The plurality of heat sink interconnects is located adjacent the high-power die in a horizontal direction.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Inventors: Jose MOREIRA, Markus VALTERE, Juergen PORTMANN, Jeroen BIELEN
  • Patent number: 9300270
    Abstract: An RF device includes a substrate and a series circuit of a tunable RF component and a DC blocking capacitor. The series circuit is arranged on the substrate and couples an RF signal terminal to a fixed voltage terminal that is electrically isolated from the RF signal terminal. The tunable RF component is coupled to the RF signal terminal, the DC blocking capacitor is coupled to the fixed voltage terminal and a driver terminal is coupled to the tunable RF component.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 29, 2016
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Zidong Liu, Klaus Reimann, Kevin R. Boyle, Maurice de Jongh, Jeroen Bielen
  • Publication number: 20130335168
    Abstract: An RF device includes a substrate and a series circuit of a tunable RF component and a DC blocking capacitor. The series circuit is arranged on the substrate and couples an RF signal terminal to a fixed voltage terminal that is electrically isolated from the RF signal terminal. The tunable RF component is coupled to the RF signal terminal, the DC blocking capacitor is coupled to the fixed voltage terminal and a driver terminal is coupled to the tunable RF component.
    Type: Application
    Filed: December 23, 2010
    Publication date: December 19, 2013
    Applicant: EPCOS AG
    Inventors: Zidong Liu, Klaus Reimann, Kevin R. Boyle, Maurice de Jongh, Jeroen Bielen
  • Patent number: 8067840
    Abstract: The power amplifier module comprises a laminate substrate comprising thermal vias and terminals, as well as a platform device with an interconnection substrate of a semiconductor material. This substrate is provided with electrical interconnects at a first side, and having been mounted on the laminate substrate with an opposite second side. Electrically conducting connections extend from the first to the second side through the substrate. A power amplifier device is attached to the second side of the substrate. One of the electrically conducting connection through the interconnection substrate is a grounding path for the power amplifier, while a thermal path is provided by the semiconductor material. There is an optimum thickness for the interconnection substrate, at which both a proper grounding and a acceptable thermal dissipation is effected.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: November 29, 2011
    Assignee: NXP B.V.
    Inventors: Jeroen A. Bielen, Marcus H. Van Kleef, Freerk E. Van Straten
  • Publication number: 20100059879
    Abstract: The power amplifier module comprises a laminate substrate comprising thermal vias and terminals, as well as a platform device with an interconnection substrate of a semiconductor material. This substrate is provided with electrical interconnects at a first side, and having been mounted on the laminate substrate with an opposite second side. Electrically conducting connections extend from the first to the second side through the substrate. A power amplifier device is attached to the second side of the substrate. One of the electrically conducting connection through the interconnection substrate is a grounding path for the power amplifier, while a thermal path is provided by the semiconductor material. There is an optimum thickness for the interconnection substrate, at which both a proper grounding and a acceptable thermal dissipation is effected.
    Type: Application
    Filed: June 15, 2007
    Publication date: March 11, 2010
    Applicant: NXP B.V.
    Inventor: Jeroen A. Bielen