Abstract: According to a first aspect of the present invention there is provided a QFN packaged semiconductor device having a QFN bottom surface, the QFN packaged semiconductor device comprising: a die pad on the QFN bottom surface; a die on the die pad; a plurality of leads spaced apart from the die pad and around a periphery of the QFN bottom surface; a plurality of bond wires connecting the die and the leads; a molding compound covering the die and the bond wires, which having an central region and a peripheral region, each central region having a first top surface and first side faces, each peripheral region having a second top surface and second side faces, wherein the height of the peripheral region is lower than that of the central region.

Abstract: An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.

Abstract: An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

Abstract: One embodiment of a packaged semiconductor device includes: a redistributed layer (RDL) structure formed over an active side of a semiconductor die embedded in mold compound, the RDL structure includes a plurality of solder ball pads that in turn includes: a set of first solder ball pads located on a front side of the packaged semiconductor device within a footprint of the semiconductor die, and a set of second solder ball pads located on the front side of the packaged semiconductor device outside of the footprint of the semiconductor die, each first solder ball pad includes a first center portion having a first diameter measured between opposite outer edges of the first center portion, each second solder ball pad includes a second center portion having a second diameter measured between opposite outer edges of the second center portion, and the first diameter is smaller than the second diameter.

Abstract: Embodiments are provided for a multi-die packaged semiconductor device including: a panel of embedded dies including a plurality of radio frequency (RF) dies, wherein each RF die includes RF front-end circuitry, each RF die has an active side that includes a plurality of pads, each RF die has a back side exposed in a back side of the panel; a plurality of antenna connectors formed on a subset of the plurality of pads of each RF die; and an array of antennas formed over a front side of the panel and connected to the plurality of antenna connectors.

Abstract: Embodiments are provided for a multi-die packaged semiconductor device including: a panel of embedded dies including a plurality of radio frequency (RF) dies, wherein each RF die includes RF front-end circuitry, each RF die has an active side that includes a plurality of pads, each RF die has a back side exposed in a back side of the panel; a plurality of antenna connectors formed on a subset of the plurality of pads of each RF die; and an array of antennas formed over a front side of the panel and connected to the plurality of antenna connectors.

Abstract: Embodiments are provided that include a method for fabricating a multi-die package including: placing a plurality of flip chip dies and splitter dies on the sacrificial carrier; performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier that includes test probe circuitry; testing the flip chip and splitter dies; replacing any faulty dies; overmolding the flip chip and splitter dies on the sacrificial carrier to form a panel of embedded dies; planarizing the panel of embedded dies to expose back surfaces of the embedded dies; forming a metallization layer across the back surface of the panel of embedded dies; and removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and splitter die is exposed in the front surface.

Abstract: Embodiments are provided that include a method for fabricating a multi-die package including: placing a plurality of flip chip dies and splitter dies on the sacrificial carrier; performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier that includes test probe circuitry; testing the flip chip and splitter dies; replacing any faulty dies; overmolding the flip chip and splitter dies on the sacrificial carrier to form a panel of embedded dies; planarizing the panel of embedded dies to expose back surfaces of the embedded dies; forming a metallization layer across the back surface of the panel of embedded dies; and removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and splitter die is exposed in the front surface.

Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.

Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.

Abstract: Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated circuit dies are provided in a semiconductor wafer, with each integrated circuit die having: an integrated circuit within the die, a via extending from a first surface to a second surface that opposes the first surface, and first and second electrical contacts at the first surface respectively coupled to the via and to the integrated circuit. Lanes are created in a front side of the wafer between the dies, and a portion of the back side of the wafer is removed to expose the lanes. A further contact and/or via is also exposed at the backside, with the via providing an electrical signal path for coupling electrical signals through the integrated circuit die (e.g., bypassing circuitry therein).

Abstract: Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated circuit dies are provided in a semiconductor wafer, with each integrated circuit die having: an integrated circuit within the die, a via extending from a first surface to a second surface that opposes the first surface, and first and second electrical contacts at the first surface respectively coupled to the via and to the integrated circuit. Lanes are created in a front side of the wafer between the dies, and a portion of the back side of the wafer is removed to expose the lanes. A further contact and/or via is also exposed at the backside, with the via providing an electrical signal path for coupling electrical signals through the integrated circuit die (e.g., bypassing circuitry therein).

Abstract: The present invention relates to a lighting device (1). The lighting device comprises a light source (3), a circuit board (7) configured to control the light source, and a circuit board frame (10) comprising a slot (12). Further, an edge (8) of the circuit board is mounted in the slot such that the circuit board is in thermal contact with the circuit board frame, thereby enabling heat to be conducted from the circuit board to the circuit board frame. The present invention is advantageous in that the thermal performance of the lighting device is improved and manufacturing costs are reduced.

Abstract: The present invention relates to a lighting device (1). The lighting device comprises alight source (3), a circuit board (7) configured to control the light source, and a circuit board frame (10) comprising a slot (12). Further, an edge (8) of the circuit board is mounted in the slot such that the circuit board is in thermal contact with the circuit board frame, thereby enabling heat to be conducted from the circuit board to the circuit board frame. The present invention is advantageous in that the thermal performance of the lighting device is improved and manufacturing costs are reduced.