Abstract: An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities. Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided.

Abstract: The present disclosure describes a system-on-chip (SoC) including a built-in self-test (BIST) block, a low-dropout (LDO) voltage regulator with a pass metal-oxide-semiconductor field-effect transistor (MOSFET), and a current-monitor circuit with a sensing MOSFET, a tuning MOSFET, a sensing resistor, and a tuning resistor. Herein, both the pass MOSFET and the sensing MOSFET receive an input voltage, and a gate of the pass MOSFET is coupled to a gate of the sensing MOSFET. The sensing MOSFET, the tuning MOSFET, and the sensing resistor are connected in series between the input voltage and ground, and the tuning resistor is coupled between a gate of the tuning MOSFET and ground. The BIST block is configured to tune a current through the tuning resistor so as to adjust a voltage at a connection point of the sensing MOSFET and the tuning MOSFET.

Abstract: Systems and methods provide for testing a capacitor. The method includes: selecting a capacitor to be tested; generating an frequency signal from a source voltage which passes through a resistor, while connecting and disconnecting the capacitor, which results in an output signal; and measuring a relative level of a sideband associated with the output signal to estimate a size of the selected capacitor.

Abstract: A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Abstract: A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Abstract: The present invention discloses an integrated circuit (200) including a module (130) for processing a radio-frequency (RF) signal during normal operation of the integrated circuit. The IC (200) has an on-chip test arrangement for generating an accurate RF test signal for testing the module (130) in a test mode. To this end, the test arrangement comprises a signal source (210) for generating a radio-frequency control signal in the test mode and a complementary transistor pair (230) arranged in series, said pair being coupled between a first supply rail and a second supply rail, and being arranged to generate the radio-frequency test signal on its output in response to the radio-frequency control signal supplied to its control terminals. The invention is based on the realization that if a stable enough supply voltage is provided to the transistor pair, the pair can be forced to produce an accurate rail-to-rail voltage swing at RF frequencies on its output.

Abstract: Method and system are disclosed for modulating a radio frequency carrier signal. The radio frequency carrier signal is modulated using a VCO running at a center frequency of 0 Hz. A baseband signal is used to adjust the overall frequency of the VCO. The output of the VCO is a complex baseband signal having in-phase and quadrature components. The in-phase and quadrature components of the baseband signal arc used to modulate the in-phase and quadrature components of the radio frequency carrier signal, respectively.