Abstract: A switch protection circuit includes a discharging circuit and, optionally, a clamping circuit. The discharge circuit operates prior to the switch completing the switching action to discharge capacitance from a signal line of a cable connected to a device under test to a ground voltage. When not discharging, the discharge circuit presents low leakage to a measurement circuit so as not to interfere with such measurement. If present, the clamping circuit clamps a signal line of the cable to a guard structure of the cable so that the discharge circuit can couple both the signal line and the guard structure to ground. The protection circuit operates without significantly worsening low current performance of the measurement instrument.

Abstract: A switch protection circuit includes a discharging circuit and, optionally, a clamping circuit. The discharge circuit operates prior to the switch completing the switching action to discharge capacitance from a signal line of a cable connected to a device under test to a ground voltage. When not discharging, the discharge circuit presents low leakage to a measurement circuit so as not to interfere with such measurement. If present, the clamping circuit clamps a signal line of the cable to a guard structure of the cable so that the discharge circuit can couple both the signal line and the guard structure to ground. The protection circuit operates without significantly worsening low current performance of the measurement instrument.

Abstract: Provided is a method and system for distributing a test recipe to a tester for conducting a test to determine if a device under test operates as designed. The method includes storing an active test recipe in an active memory in local communication with the tester, and initiating the test of the device under test to be performed by the tester according to a parameter included in the active test recipe stored in the active memory. A second parameter included in a second test recipe is received by the tester while conducting the test of the device under test according to the parameter included in the active test recipe. The method further includes storing the second parameter in a buffer memory in local communication with the active memory, and initiating a transfer of the second parameter from the buffer memory to the active memory.

Abstract: Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.