Patents by Inventor Jerold Lee

Jerold Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134510
    Abstract: An electronic device is disclosed. The electronic device can include an electronic component. The electronic device can include a shaped body in which the electronic component is at least partially embedded, the shaped body comprising a base portion and a plurality of heat-dissipating projections extending outwardly therefrom. In some embodiments, the electronic device can include a passive electronic device, such as an inductor or transformer.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 6, 2021
    Inventors: Michael John Anderson, George Anthony Serpa, Jerold Lee
  • Patent number: 7692276
    Abstract: Methods, systems, and apparatuses for integrated circuit packages, such as ball grid array packages, and processes for assembling the same, are provided. A first strip includes an array of package substrate sections. An IC die is mounted to each package substrate section of the first strip. A second strip includes an array of leadframe sections. The second strip is positioned adjacent to the first strip to couple a planar protruding area of each leadframe section to a corresponding IC die mounted to the first strip. An encapsulating material is applied to the adjacently positioned first and second strips to fill a space between the first and second strips and to fill a cavity in a top surface of each leadframe section. A planar region of the first strip surrounding each centrally located cavity is not covered by the encapsulating material. The adjacently positioned first and second strips are singulated into a plurality of IC packages.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: April 6, 2010
    Assignee: Broadcom Corporation
    Inventor: Jerold Lee
  • Publication number: 20090039485
    Abstract: Methods, systems, and apparatuses for integrated circuit packages, such as ball grid array packages, and processes for assembling the same, are provided. A first strip includes an array of package substrate sections. An IC die is mounted to each package substrate section of the first strip. A second strip includes an array of leadframe sections. The second strip is positioned adjacent to the first strip to couple a planar protruding area of each leadframe section to a corresponding IC die mounted to the first strip. An encapsulating material is applied to the adjacently positioned first and second strips to fill a space between the first and second strips and to fill a cavity in a top surface of each leadframe section. A planar region of the first strip surrounding each centrally located cavity is not covered by the encapsulating material. The adjacently positioned first and second strips are singulated into a plurality of IC packages.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Applicant: BROADCOM CORPORATION
    Inventor: Jerold Lee
  • Patent number: 6819176
    Abstract: A high bandwidth operational amplifier architecture has three control loops, which are combined via a voltage-follower-configured field effect transistor. The first control loop is an instantaneous main amplification path and employs positive feedback-based Vgs correction of the output transistor. The second control loop has a bandwidth considerably lower than the first loop and employs negative feedback to correct for long term drift errors. The third control loop, utilizing negative feedback, is a fast path having a bandwidth that overlaps the bandwidth of the first control loop, and corrects for overshoot and undershoot in the main amplification path.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: November 16, 2004
    Assignee: Remec, Inc.
    Inventor: Jerold Lee
  • Patent number: 6462627
    Abstract: The present invention, generally speaking, allows for a substantial reduction in oscillator phase noise by modifying the transfer function of a portion of the oscillator, e.g., by adding a zero to the transfer function. Modifying the transfer function reduces the open-loop gain of the oscillator but achieves a desired phase compensation, allowing the oscillator to be operated at the resonance of the resonator instead of off resonance. In an exemplary embodiment, the transfer function is modified by choosing a capacitance value such that, instead of operating as a bypass at the frequency of interest, adds a zero to the transfer function of the oscillator and causes a change in frequency characteristics, achieving an increase in the effective Q of the oscillator. This increase in effective Q translates directly into reduced phase noise. Phase noise improvement in the range of 3dB has been demonstrated.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: October 8, 2002
    Assignee: Tropian Inc.
    Inventor: Jerold Lee