Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet. As a result, the configuration manager determines that a direct connection exists between the first device's outbound port and the second device's inbound port. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers that correspond to the first device and the second device, respectively.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet. As a result, the configuration manager determines that a direct connection exists between the first device's outbound port and the second device's inbound port. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers that correspond to the first device and the second device, respectively.

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film.

Abstract: Discrete computational elements are provided that will be connected to a base unit, and to one another or I/O devices, in order to configure a particular computer system. The base unit provides the electrical power required to energize the computational elements. A plurality of identically configured substrates are joined in a layered relation and are electrically connected with one another. These substrates are capable of being fabricated of different lengths such that they can extend outwardly from the computational element and may be connected to other computational elements. At least one integrated circuit will be placed on one side of the joined substrates and is electrically connected to each substrate layer. In this manner the ICs will be able to communicate with chips on other computational elements.

Abstract: A memory module is built up from a power distribution assembly in the form of plates forming a capacitor of low inductance and a flexible circuit substrate. The circuit substrate is populated with precisely positioned contact pads for the power, read, write and address lines of memory chips that contact the substrate. Memory chips are fixed to heat spreaders and loaded into a chip holder which positions the chips for contact with the contact pads on the substrate. The substrate contact pads are plated to form dendritic crystals of palladium and the memory chips are provided with solder balls on the contact pads of the memory chip. The solder balls are held in contact with the contact pads by the compressive forces of clamping a heat sink over the heat spreaders for testing, and the assembly may be readily disassembled to replace any defective memory. The compression connection of the chips to the substrate may be relied on or the solder balls may be reflowed to establish permanent solder connections.

Abstract: A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate.

Abstract: A method of fabricating a substrate module is provided that includes cavities of a diameter and depth which take into account the statistical variance in the dimensions of C4 solder balls. By constructing cavities with the proper dimensions, electrical connection between the chip and substrate, via the solder balls, can be ensured. Further, an annular shoulder is provided which acts as a positive stop to prevent any over travel of the C4s within the cavity, thereby allowing a great deal more pressure to be applied to seat the chip than possible with conventional methods. The present invention also provides processes for applying a coating of material onto the substrate which acts as an adhesive and sealant. This material is provided intermediate any of the holes or cavities (vias) which may be contained within the substrate, and is not deposited in these vias such that no interference is encountered when attaching the chip by way of the C4 solder balls thereon.

Abstract: A power management circuit for operating a magnetic repulsion punch comprising a storage capacitor arranged to be connected in parallel with an inductive load serving as an operating coil of the magnetic repulsion punch, a means for selectively and temporarily coupling the inductive load to the storage capacitor for forming a resonant circuit, and a means for charging the storage capacitor after each operation.

Abstract: This invention provides a heat sink assembly for cooling electrical and electronic circuits. A low cost assembly method is achieved by a pivotal assembly containing a heat sink which snaps into place adjacent to an electrical/electronic circuit which requires cooling. The snap-in heat sink assembly contains a resilient heat transfer material which is exposed to the devices requiring heat removal by windows or other openings in a plate which is disposed between the heat transfer material and the snap-in frame.

Abstract: A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate. This card can then be used in the manufacture of an electronic device without the necessity of reworking the burned-in ICs. Further, if any of the chips fail the burn-in testing, the time and overhead required for reworking is minimized since the chips are not permanently attached.

Abstract: A system is provided which utilizes a plurality of sequentially controlled magnetic repulsion punches arranged in a variable array to punch a constantly moving substrate. These punches are disposed adjacent the constant velocity substrate on which holes, or vias are formed as the punches are sequentially fired. The array of punches is placed at an angle with respect to the perpendicular of the direction of movement of the substrate. Thus, a delay is present between the time when the first punch must be fired and the firing of subsequent punches, due to the angle of the array. Therefore, due to this delay between the time the first punch must energized, and the energizing of subsequent punches a single power supply is capable of providing energy to a group of punches.

Abstract: A multilayer, flexible substrate upon which integrated circuit chips can be attached is disclosed. The input/output(I/O) connections from the chip do not radiate outward from the side of the die, but rather extend from a bottom surface. Since the I/O signal lines would not be accessible for testing once the IC chip is mounted on a substrate, each I/O line is extended outward from the IC footprint to an area on the substrate which is accessible. Additionally, an electrical path from each I/O signal port is simultaneously passed through the substrate layers upon which the chip is mounted, thus providing electrical contact of all I/O ports to the underside of the flexible substrate.An integrated circuit chip is mounted on this flexible substrate. Since each I/O line is accessible after mounting, the IC chip can be tested prior to mounting on its ultimate carrier. Once tested, the IC chip and the substrate upon which it is mounted are excised from the roll of substrate material.

Abstract: An interconnect strip is provided for effecting electrical interconnection between pluralities of conductor pads disposed on circuit boards or the like in a high density configuration. The strip is fabricated from a polymer film carrier having laminated thereon a metal foil with preselected spring properties. After lamination, lithographic techniques from a series of electrically isolated metallic beams on the carrier. Additional chemical processing removes portions of the carrier at opposing sides of the strip to expose opposing ends of the beams which extend beyond the carrier parallel to one another in opposing directions outwards from the carrier. By urging the pads towards respective beam ends of the strip disposed between the pads until mating engagement therewith, a plurality of electrical interconnections are established through the beams.