Patents by Inventor Jerome Albert Frankeny

Jerome Albert Frankeny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6098282
    Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jerome Albert Frankeny, Richard Francis Frankeny, Terry Frederick Hayden, Ronald Lann Imken, Janet Louise Rice
  • Patent number: 5770891
    Abstract: A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: June 23, 1998
    Assignee: International Business Machines Corporation
    Inventors: Richard Francis Frankeny, Jerome Albert Frankeny, Danny Edward Massey, Keith Allan Vanderlee
  • Patent number: 5745333
    Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: April 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Jerome Albert Frankeny, Richard Francis Frankeny, Terry Frederick Hayden, Ronald Lann Imken, Janet Louise Rice
  • Patent number: 5691041
    Abstract: A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: November 25, 1997
    Assignee: International Business Machines Corporation
    Inventors: Richard Francis Frankeny, Jerome Albert Frankeny, Danny Edward Massey, Keith Allan Vanderlee