Patents by Inventor Jerome Alieu

Jerome Alieu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Photosensitive integrated circuit equipped with a reflective layer and corresponding method of production
    Patent number: 8610048
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Jerome Alieu, Simon Guillaumet, Christophe Legendre, Hughes Leininger, Jean-Pierre Oddou, Marc Vincent
  • Photosensitive integrated circuit equipped with a reflective layer and corresponding method of production
    Publication number: 20070138470
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Application
    Filed: November 21, 2006
    Publication date: June 21, 2007
    Inventors: Jerome Alieu, Simon Guillaumet, Christophe Legendre, Hugues Leininger, Jean-Pierre Oddou, Marc Vincent
  • Process for achieving intermetallic and/or intrametallic air isolation in an integrated circuit, and integrated circuit obtained
    Patent number: 6812113
    Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics SA
    Inventors: Jerome Alieu, Christophe Lair, Michel Haond