Abstract: A metal oxide varistor comprising one or more zinc oxide layers is formed integral to a ceramic substrate to provide ESD protection of a semiconductor device mounted to the substrate. The portion of the ceramic substrate not forming the varistor may be aluminum oxide, aluminum nitride, silicon carbide, or boron nitride. The varistor portion may form any part of the ceramic substrate, including all of the ceramic substrate.

Abstract: One or more circuit elements such as silicon diodes, resistors, capacitors, and inductors are disposed between the semiconductor structure of a semiconductor light emitting device and the connection layers used to connect the device to an external structure. In some embodiments, the n-contacts to the semiconductor structure are distributed across multiple vias, which are isolated from the p-contacts by one or more dielectric layers. The circuit elements are formed in the contacts-dielectric layers-connection layers stack.

Abstract: A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A first contact electrically contacts the layer of first conductivity type through the via. A second contact electrically contacts the layer of second conductivity type. A ring that surrounds the light emitting layer and is electrically connected to the first contact electrically contacts the layer of first conductivity type.

Abstract: A relatively small ESD protection diode is formed on the same chip as a light emitting diode. In one embodiment, the ESD diode is a mesa-type diode isolated from the light emitting diode by a trench. To reduce the series resistance of the ESD diode, the PN junction and metal contact to the semiconductor material is made long and expands virtually the width of the chip. Various configurations of the PN junction and the N and P metal contacts for the ESD diode are described for increasing the breakdown voltage and for improved testing.

Abstract: A metal oxide varistor comprising one or more zinc oxide layers is formed integral to a ceramic substrate to provide ESD protection of a semiconductor device mounted to the substrate. The portion of the ceramic substrate not forming the varistor may be aluminum oxide, aluminum nitride, silicon carbide, or boron nitride. The varistor portion may form any part of the ceramic substrate, including all of the ceramic substrate.

Abstract: A mount for a semiconductor light emitting device includes an integrated reflector cup. The reflector cup includes a wall formed on the mount and shaped and positioned to reflect side light emitted from the light emitting device along a vertical axis of the device/mount combination. The wall may be covered by a reflective material such as a reflective metal.

Abstract: A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A first contact electrically contacts the layer of first conductivity type through the via. A second contact electrically contacts the layer of second conductivity type. A ring that surrounds the light emitting layer and is electrically connected to the first contact electrically contacts the layer of first conductivity type.

Abstract: A device includes a submount, and a semiconductor light emitting device mounted on first and second conductive regions on a first side of the submount in a flip chip architecture configuration. The submount has third and fourth conductive regions on a second side of the submount. The third and fourth conductive regions may be used to solder the submount to structure such as a board, without the use of wire bonds. The first and third conductive regions are electrically connected by a first conductive layer and the second and fourth conductive regions are electrically connected by a second conductive layer. The first and second conductive layers may be disposed on the outside of the submount or within the submount.