Abstract: An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses. Finally, the device also comprises control circuitry (14, 16), operable during an overflow condition of the memory structure, for writing each data word in successive ones of received data words across multiple ones of the memory word addresses.

Abstract: A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.

Abstract: An electronic device (10). The device comprises a memory structure (12), which comprises an integer M of memory word slots. Each memory word slot is operable to store an integer N of bits. The device also comprises a scan storage circuit (18), operable to receive a scan word having a number of bits less than M×N. The device also comprises control circuitry (16) for causing successive scan words to be written into the scan storage circuit, for causing successive scan words to be written from the scan storage circuit into the memory structure, and for causing successive scan words to be read from the memory structure into the scan storage circuit.

Abstract: An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses.

Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.

Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.

Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.

Abstract: The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term "pseudo-scan" is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a "dummy" circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.

Abstract: A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.