Abstract: An example apparatus, a computer-implemented method for encoding a coordinate locations, and an imaging sensor comprising location encoding circuitry are provided. The example apparatus includes location encoding circuitry configured to receive a coordinate location associated with a location in a coordinate system; determine a sequential distance between the coordinate location and a previous coordinate location, wherein the sequential distance indicates a number of positions in a sequential order between the coordinate location and the previous coordinate location; determine a step size based on a plurality of coordinate locations; and determine a coordinate location encoding associated with the coordinate location based on a comparison of the sequential distance to the step size.

Abstract: An electronic device includes a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks, a second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks, and a third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks. A processor is coupled to receive output signals on the first and second output tracks. The output signals from the test pixels of the second and third arrays are fixed at one or the other of only two values in the absence of a defect. The output signals received by the processor over the first and second output tracks are processed to determine presence or absence of a defect.

Abstract: An electronic device includes a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks, a second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks, and a third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks. A processor is coupled to receive output signals on the first and second output tracks. The output signals from the test pixels of the second and third arrays are fixed at one or the other of only two values in the absence of a defect. The output signals received by the processor over the first and second output tracks are processed to determine presence or absence of a defect.

Abstract: An image device has an array of pixels, each pixel having a photosensitive area, a first storage node and a second storage node. A pixel is illuminated for a first period of time, and charge accumulated on the photosensitive area of the pixel during the first period of time is stored on the first storage node of the pixel. The pixel of the array is illuminated for a second period of time, and charge accumulated on the photosensitive area during the second period of time is stored on the second storage node of the pixel. A first signal is generated based on the charge stored on the first storage node, and a second signal is generated based on the charge stored on the second storage node. The first and second signals are combined using at least one subtraction operation having the first and second signals as operands.

Abstract: An electronic circuit includes a clock signal generator configured to deliver a clock signal. A propagation circuit is configured to propagate the clock signal on a plurality of propagation branches. A number of timers are coupled to at least some of the branches. The timers are clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal. A comparator is configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another.

Abstract: An image device has an array of pixels, each pixel of the array having a photosensitive area, a first storage node and a second storage node. A pixel of the array is illuminated for a first period of time, and charge accumulated on the photosensitive area of the pixel during the first period of time is stored on the first storage node of the pixel. The pixel of the array is illuminated for a second period of time, and charge accumulated on the photosensitive area during the second period of time is stored on the second storage node of the pixel. A first signal is generated based on the charge stored on the first storage node, and a second signal is generated based on the charge stored on the second storage node. The first and second signals are combined using at least one subtraction operation having the first and second signals as operands.

Abstract: An electronic circuit includes a clock signal generator configured to deliver a clock signal. A propagation circuit is configured to propagate the clock signal on a plurality of propagation branches. A number of timers are coupled to at least some of the branches. The timers are clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal. A comparator is configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another.

Abstract: A three dimensional (3D) device is formed from a first level and a second level that are attached together. The first level includes a backside illuminated two dimensional (2D) image sensor including an array of first pixels sensitive to visible light. The second level includes a frontside illuminated depth sensor including an array of second pixels sensitive to near infrared light. The first and second levels are attached in a manner such that radiation, in particular the near infrared light, received at the backside of the first level passes through the first level to reach the depth sensor in the second level.

Abstract: An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.

Abstract: A three dimensional (3D) device is formed from a first level and a second level that are attached together. The first level includes a backside illuminated two dimensional (2D) image sensor including an array of first pixels sensitive to visible light. The second level includes a frontside illuminated depth sensor including an array of second pixels sensitive to near infrared light. The first and second levels are attached in a manner such that radiation, in particular the near infrared light, received at the backside of the first level passes through the first level to reach the depth sensor in the second level.

Abstract: An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.

Abstract: A device for correcting the optical response of a flat screen display system. This device comprises a gamma correction circuit of a type currently used for the correction of the optical response of cathode-ray display systems.