Abstract: A device implementing adaptive gain table selection based at least on coexistence signaling may include at least one processor circuit. The at least one processor circuit may be configured to identify that a packet is scheduled to be received by a receiver and retrieve at least one transmission indicator that indicates whether at least one transmitter is transmitting, where the at least one transmitter is collocated with the receiver within a device. The at least one processor circuit may be further configured to select a first gain table for reception of the packet by the receiver when the at least one transmission indicator indicates that the at least one transmitter is transmitting, otherwise selecting a second gain table for reception of the packet by the receiver. The at least one processor circuit may be further configured to apply gain to the receiver based at least on the selected gain table.

Abstract: A device implementing adaptive gain table selection based at least on coexistence signaling may include at least one processor circuit. The at least one processor circuit may be configured to identify that a packet is scheduled to be received by a receiver and retrieve at least one transmission indicator that indicates whether at least one transmitter is transmitting, where the at least one transmitter is collocated with the receiver within a device. The at least one processor circuit may be further configured to select a first gain table for reception of the packet by the receiver when the at least one transmission indicator indicates that the at least one transmitter is transmitting, otherwise selecting a second gain table for reception of the packet by the receiver. The at least one processor circuit may be further configured to apply gain to the receiver based at least on the selected gain table.

Abstract: A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (IC) at a first voltage and first frequency. A test program is executed by a central processing unit (CPU) comprised within the IC to test a portion of the IC. Communication activity between the IC and a host system is recorded to form a data log while the test program is being executed. A crash is detected by storing and examining the data log periodically, and assuming that the test program has crashed when any one of a predetermined set of crash conditions is detected during examination of the data log. The operating point may be iteratively changed and execution of the test program repeated while continuing to check for a crash until a crash is detected.

Abstract: A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (IC) at a first voltage and first frequency. A test program is executed by a central processing unit (CPU) comprised within the IC to test a portion of the IC. Communication activity between the IC and a host system is recorded to form a data log while the test program is being executed. A crash is detected by storing and examining the data log periodically, and assuming that the test program has crashed when any one of a predetermined set of crash conditions is detected during examination of the data log. The operating point may be iteratively changed and execution of the test program repeated while continuing to check for a crash until a crash is detected.