Patents by Inventor Jerome F. Lapham
Jerome F. Lapham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6005282Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.Type: GrantFiled: January 18, 1995Date of Patent: December 21, 1999Assignee: Analog Devices, Inc.Inventors: Jerome F. Lapham, Brad W. Scharf
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Patent number: 5759902Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.Type: GrantFiled: March 18, 1996Date of Patent: June 2, 1998Assignee: Analog Devices, IncorporatedInventors: Jerome F. Lapham, Brad W. Scharf
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Patent number: 5529939Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.Type: GrantFiled: November 4, 1994Date of Patent: June 25, 1996Assignee: Analog Devices, IncorporatedInventors: Jerome F. Lapham, Brad W. Scharf
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Patent number: 5479316Abstract: An integrated circuit metal-oxide-metal capacitor and method of making it which involves a support layer; a first conductive electrode on the support layer; a dielectric film on the first conductive electrode; a second conductive electrode disposed on the dielectric film and formed from the first level metallization interconnect layer of the integrated circuit; an interlevel dielectric layer; a first contact via extending through the interlevel dielectric layer and the dielectric film to the first conductive electrode; a second contact via extending through the interlevel dielectric layer to the second conductive electrode; and first and second terminals formed from the second level metallization interconnect layer of the integrated circuit contacting the first and second vias, respectively.Type: GrantFiled: August 24, 1993Date of Patent: December 26, 1995Assignee: Analog Devices, Inc.Inventors: Mark A. Smrtic, George M. Molnar, Jerome F. Lapham
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Patent number: 5319227Abstract: A low-leakage-current JFET having electrically isolated top and bottom gates. The structure employs enclosed geometry wherein one source/drain region fully surrounds the other source/drain region. Connection to the top gate is made through a diffusion-barrier to prevent penetration of metallization into the top gate contact region. A non-penetrating contact layer is provided on the upper surface of the top gate so that the material of the contact layer does not enter the top gate region to any significant extent. Both the channel region and the shield layer are formed by ion-implantation.Type: GrantFiled: March 12, 1992Date of Patent: June 7, 1994Assignee: Analog Devices, IncorporatedInventors: Jerome F. Lapham, Adrian P. Brokaw
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Patent number: 5302848Abstract: A process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and a novel chip made by such a process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.Type: GrantFiled: March 1, 1993Date of Patent: April 12, 1994Assignee: Analog Devices, Inc.Inventors: Jerome F. Lapham, Brad W. Scharf
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Patent number: 5141898Abstract: An integrated-circuit (IC) chip having means to prevent or mitigate damage from electrostatic discharge (ESD) employing a thick dielectric coating of insulative oxide between the surface of the chip substrate and the metallization film used to make contact with regions of the substrate. At least a portion of this layer is formed at temperatures below 700.degree. C. The coating is sufficiently thick everywhere that its breakdown voltage is greater than the breakdown voltage of any junction in the substrate. This assures that the breakdown caused by ESD will always occur in the junction, which is self healing, rather than in the dielectric coating, where the damage could be permanent.Type: GrantFiled: September 27, 1991Date of Patent: August 25, 1992Assignee: Analog Devices, IncorporatedInventor: Jerome F. Lapham
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Patent number: 5065214Abstract: An integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, is disclosed. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.Type: GrantFiled: November 1, 1989Date of Patent: November 12, 1991Assignee: Analog Devices, IncorporatedInventors: Jerome F. Lapham, Brad W. Scharf
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Patent number: 4985739Abstract: A low-leakage-current JFET having electrically isolated top and bottom gates. The structure employs enclosed geometry wherein one source/drain region fully surrounds the other source/drain region. Connection to the top gate is made through a diffusion-barrier to prevent penetration of metallization into the top gate contact region. A non-penetrating contact layer is provided on the upper surface of the top gate so that the material of the contact layer does not enter the top gate region to any significant extent. Both the channel region and the shield layer are formed by ion-implantation.Type: GrantFiled: April 27, 1987Date of Patent: January 15, 1991Assignee: Analog Devices, IncorporatedInventors: Jerome F. Lapham, Adrian P. Brokaw
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Patent number: 4969823Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.Type: GrantFiled: May 5, 1988Date of Patent: November 13, 1990Assignee: Analog Devices, IncorporatedInventors: Jerome F. Lapham, Brad W. Scharf
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Patent number: 4399345Abstract: A method of laser trimming thin film resistors on semiconductive substrates wherein the laser is set to a frequency equal to or less than E.sub.g /h, where E.sub.g is the optical band-gap energy of the doped semiconductor substrate, and h is Planck's constant.Type: GrantFiled: June 9, 1981Date of Patent: August 16, 1983Assignee: Analog Devices, Inc.Inventors: Jerome F. Lapham, Tommy D. Clark