Abstract: Example embodiments disclosed herein relate to touch screen selection. A device displays a plurality of touch elements on a touch-enabled display. The device receives a touch input via the touch-enabled display. Further, the device determines an ambiguity based on the touch selection input. The device magnifies an area associated with the touch selection input based on the ambiguity determination. Moreover, the area includes a set of the touch elements associated with the ambiguity termination. The device receives another touch input at the area via the touch-enabled display. Then, the device determines one of the touch elements based on the other touch input.

Abstract: Example embodiments disclosed herein relate to touch screen selection. A device displays a plurality of touch elements on a touch-enabled display. The device receives a touch input via the touch-enabled display. Further, the device determines an ambiguity based on the touch selection input. The device magnifies an area associated with the touch selection input based on the ambiguity determination. Moreover, the area includes a set of the touch elements associated with the ambiguity termination. The device receives another touch input at the area via the touch-enabled display. Then, the device determines one of the touch dements based on the other touch input.

Abstract: A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Abstract: A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Abstract: There is provided a cache that includes a cache line, and an indicator associated with a unit-sized portion of the cache line. The indicator indicates whether the unit-sized portion is accessed. A method for determining an arrangement of data in a memory for efficient operation of a cache includes determining whether the unit of the data is accessed during an execution of code, and compiling the code to place the unit in a line of the memory if the unit is accessed during the execution. The line of the memory is designated to contain, in contiguous locations, a plurality of units of the data that are accessed during the execution.

Abstract: A system of the present invention utilizes memory for storing a computer program and processing circuitry for processing and executing instructions of the computer program. In particular, the computer program includes a set of code and an unconditional branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry receives and processes the unconditional branch instruction. When the set of code is disabled, the processing circuitry executes the unconditional branch instruction based on the mode indicator, thereby preventing execution of the set of code. However, when the set of code is enabled, the processing circuitry refrains from executing the unconditional branch instruction based on the mode indicator and executes the set of code.

Abstract: The system of the present invention utilizes memory for storing a computer program and processing circuitry for executing instructions of the computer program. In particular, the computer program includes at least one branch instruction and a set of code that is to be selectively enabled or disabled. The branch instruction includes an address identifier identifying a memory address to which the processing circuitry may branch when executing the branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry executes the branch instruction. In executing the branch instruction, the processing circuitry, depending on the value of the mode indicator, branches to the address identified by address identifier or branches to a different address.