Abstract: A voltage level shifting driver and receiver for interfacing systems using ositive logic levels and systems using negative logic levels. The driver operates to convert positive voltage logic levels to negative voltage logic levels and the receiver operates to convert negative voltage logic levels back to positive voltage logic levels.

Abstract: A serial-to-parallel data conversion and synchronization scheme in which a lurality of active logic elements are utilized as delay lines. Each of the delay lines introduces a delay equal to the period of one data bit and one additional delay line introduces a delay equal to one half the period of a data bit. The input of the first delay line is connected to the data input of a first flip-flop and the outputs of each of the plurality of delay lines are each connected to the data input of a flip-flop. The output of the additional delay line is connected to the clock inputs of each of the flip-flops whereby the serial data word is converted to a parallel data word and the conversion is internally clocked by the delay lines themselves.