Patents by Inventor Jerome J. Witalka

Jerome J. Witalka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5659794
    Abstract: A network input/output processing system for sending and receiving messages between a large scale computer system and associated communications networks. Executive operating system services provide access to a control table, an input queue, and an output queue stored in the computer system's main memory. A network input/output processor responds to requests by application programs, through a communications program, for receiving input from and sending output to a network, concurrently with requests to communicate with directly attached peripheral devices such as disk drives, tape drives, and printers. The network input/output processor receives initialization, reset, and termination requests via the control table. Requests to receive input are received from the input queue. Input data is stored into buffers as directed by the input request. Requests to send output are received from the output queue. Output data is read from the buffers as directed by the output request.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: August 19, 1997
    Assignee: Unisys Corporation
    Inventors: Charles R. Caldarale, Peter J. Hancock, David R. Johnson, Robert M. Malek, James R. McBreen, Hans C. Mikkelsen, Jerome J. Witalka
  • Patent number: 4511967
    Abstract: The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM)) both within a remote slave digital logic device (called a CENTRAL COMPLEX) is bit-serially conducted upon one signal line of a scan/set network by a controlling digital logic device (called a SUPPORT PROCESSOR) in substantially simultaneous time to the reading of the previous contents of such register (and control store) bit-serially via another signal line of said scan/set network. Both signal lines and devices together form a circular BIT-SERIAL SCAN LOOP, upon which the bit-serial writing and reading is time overlapped.
    Type: Grant
    Filed: February 15, 1983
    Date of Patent: April 16, 1985
    Assignee: Sperry Corporation
    Inventors: Jerome J. Witalka, Howard L. Buettner, James G. Ellsworth
  • Patent number: 4437157
    Abstract: An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O ports or I/O channels for the transmission of information between the computer and peripheral devices. Improvements to these I/O channels, now common in the art, permit multiple peripheral devices to be coupled to the computer through a single I/O channel. Each of these multiple peripheral devices may be said to communicate through an I/O subchannel. A given I/O subchannel designation logically specifies the hardware within the shared I/O channel that is dedicated to communication with the corresponding one of the multiple peripheral devices coupled to that shared I/O channel. The present invention is an improvement which provides for allocation of I/O subchannels to I/O channels in the field rather than at time of manufacture.
    Type: Grant
    Filed: April 20, 1981
    Date of Patent: March 13, 1984
    Assignee: Sperry Corporation
    Inventors: Jerome J. Witalka, Duane G. Kurth, David J. Baber