Patents by Inventor Jerome Lopez

Jerome Lopez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260096464
    Abstract: A method of manufacturing an electronic device includes the following steps: providing an assembly comprising a substrate having a first die formed therein and having conductive areas positioned on a top surface thereof, a second die being mounted on the substrate and connected to the first die, the second die comprising through silicon vias; forming conductive pillars on the connection areas, an upper surface of the conductive pillars being flush with the second surface of the second die; forming a passivation layer on the substrate and on the second die; and forming conductive elements on the conductive pillars and on the vias, the periphery of the conductive elements covering the passivation layer.
    Type: Application
    Filed: October 1, 2025
    Publication date: April 2, 2026
    Applicant: STMicroelectronics International N.V.
    Inventors: Romain COFFY, Jerome LOPEZ, Julien CUZZOCREA
  • Publication number: 20250372403
    Abstract: An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.
    Type: Application
    Filed: August 20, 2025
    Publication date: December 4, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Fanny LAPORTE, Jerome LOPEZ
  • Publication number: 20250285927
    Abstract: A hydrophobic electronic component is made using a process step where a hydrophobic coating is deposited on an electronic component. That electronic component includes a substrate, a chip positioned on a first side of the substrate, electric connection terminals positioned on a second side of the substrate, electric tracks running through the substrate, and a resin or a cover covering the first side of the substrate and the chip.
    Type: Application
    Filed: March 3, 2025
    Publication date: September 11, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Ludovic FOURNEAUD, Jerome LOPEZ, Didier SIGNORET
  • Patent number: 12249549
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Grant
    Filed: April 9, 2024
    Date of Patent: March 11, 2025
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome Lopez
  • Publication number: 20250079259
    Abstract: An integrated circuit package includes a support plate having a mounting face. An electronic chip, having a rear face and a front face, is mounted on the mounting face with the front face electrically connected to the mounting face of the support plate. A deformable thermally conductive film covers at least one portion of the rear face of the electronic chip so that the film is in contact with the rear face.
    Type: Application
    Filed: September 4, 2024
    Publication date: March 6, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Jerome LOPEZ, Luc PETIT, Karine SAXOD
  • Publication number: 20250070081
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Patent number: 12218287
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: February 4, 2025
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier Zanellato, Remi Brechignac, Jerome Lopez
  • Patent number: 12170262
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 17, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Publication number: 20240258184
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome LOPEZ
  • Patent number: 11984373
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: May 14, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome Lopez
  • Publication number: 20240087977
    Abstract: An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 14, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Jerome LOPEZ
  • Publication number: 20240072214
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
  • Patent number: 11862757
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier Zanellato, Remi Brechignac, Jerome Lopez
  • Publication number: 20230411271
    Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Luc PETIT, Jerome LOPEZ, Karine SAXOD
  • Publication number: 20230290712
    Abstract: An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fanny LAPORTE, Jerome LOPEZ
  • Publication number: 20230121780
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Patent number: 11557566
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Publication number: 20220200117
    Abstract: A device for transmission of at least one high-frequency signal includes at least one first electrically-conductive track formed inside and/or on top of a flexible substrate.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Ludovic FOURNEAUD, Gregory BOUTELOUP, Jerome LOPEZ
  • Publication number: 20220157679
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 19, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome LOPEZ
  • Publication number: 20220102591
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 31, 2022
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ