Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between clock domain boundaries and for maintaining alignment of multiple outputs signals.

Abstract: Methods and structures of performing multi-level comma detection and alignment on an unaligned data stream. Each string of N consecutive bits in the unaligned data stream is monitored for a predetermined byte value. When the predetermined byte value is located, the unaligned data stream is aligned with the predetermined byte value, producing a partially aligned data stream. A string of bytes from the partially aligned data stream is then compared with a predetermined sequence of byte values. When the predetermined sequence is located, the partially aligned data stream is aligned based on the location of the predetermined sequence within the partially aligned data stream. The invention also encompasses multi-level comma detection and alignment circuits that can perform, for example, the previously described inventive methods.

Abstract: A dedicated protocol generation unit provides the ability to detect validity of data received from a configurable logic block, such as a programmable logic device (PLD). Data valid signaling is provided by the configurable logic block, such that invalid data received from the configurable logic block is replaced with programmable insertion data prior to transmission, while valid data is allowed to be transmitted without replacement. Also, data received by Input/Output (I/O) portions of the dedicated protocol generation unit are compared to programmable data patterns. After a positive comparison, matching data is either truncated and not delivered to the configurable logic block, or the matching data is delivered to the configurable logic block with appropriate data valid signaling.

Abstract: A system and method for interfacing network elements using an isolated fabric interface module, which is facilitated through exploitation of standards otherwise not specified for the particular networking functions in which they are utilized. Fabric interface functionality is isolated and independent of line and switch fabric cards. Standards otherwise suitable for use in interfacing network elements are adapted for use in the isolated fabric interface configuration. The standard interfaces are adapted to extend beyond the specified length, signal traces are routed according to predetermined routing rules using matched impedance connectors, and signals are terminated to facilitate the length extension. Standard system controllers may also be used although the controlled line cards are not compliant with the standard.

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing an oscillator input signal to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) are providing in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.